Abstract: An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal and to distribute the signal to each of the at least two logic cells.

Abstract: For application to analog, mixed-signal, and custom digital circuits, a system and method to do: global statistical optimization (GSO), global statistical characterization (GSC), global statistical design (GSD), and block-specific design. GSO can perform global yield optimization on hundreds of variables, with no simplifying assumptions. GSC can capture and display mappings from design variables to performance, across the whole design space. GSC can handle hundreds of design variables in a reasonable time frame, e.g., in less than a day, for a reasonable number of simulations, e.g., less than 100,000. GSC can capture design variable interactions and other possible nonlinearities, explicitly capture uncertainties, and intuitively display them. GSD can support the user's exploration of design-to-performance mappings with fast feedback, thoroughly capturing design variable interactions in the whole space, and allow for more efficiently created, more optimal designs.

Abstract: A method and apparatus for dewatering of effluents through the use of automated optimization using feedback control. The method and apparatus for feedback control optimizes dewatering processes for any water cleansing process that uses retention and/or flocculation aids (e.g., polymers) to impact endpoint water clarity. Disclosed implementations include processing using dissolved air flotation (DAF) and sludge cake formation. The methodology includes real-time monitoring of turbidity and incremental control of polymer to manage changes to turbidity/suspended solids due to operating parameters such as temperature, chemical variations, and mechanical influences.

Abstract: A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. Data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request.

Abstract: A segmented insulative device and related kit for insulating components of a thermal distribution system. The kit includes a sheet of segmented insulation formed by a composite layer of segmented, flexible, pre-sewn insulation that is easily cut to size in the field using scissors, utility knives or other simple, hand-held cutting devices. The kit also includes two-sided hook-and-loop straps as fasteners, also easily cut to length, using hand-held devices. The segmented insulation and the hook-and-loop straps are attached to one another in the field using a stapler or other hand-held attachment device. This provides an installation kit that an installer can use to provide a versatile insulation in the form of the assembled segmented insulative device. The segmented insulative device lends itself to quick customization on-site rather than requiring costly off-site manufacture or pre-assembly and subsequent quick installation on the pipe component requiring thermal installation.

Abstract: An integrated spectral sensing engine featuring energy sources and detectors within a single package includes sample interfacing optics and acquisition and processing electronics. The miniaturized sensor is optimized for specific laboratory and field-based measurements by integration into a handheld format. Design and fabrication components support high volume manufacturing. Spectral selectivity is provided by either continuous variable optical filters or filter matrix devices. The sensor's response covers the range from 200 nm to 25 ?m based on various solid-state detectors. The wavelength range can be extended by the use of filter-matrix devices. Measurement modes include transmittance/absorbance, turbidity (light scattering) and fluorescence (emission). On board data processing includes raw data acquisition, data massaging and the output of computed results. Sensor applications include water and environmental, food and beverage, chemical and petroleum, and medical analyses.

Abstract: A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.

Abstract: A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated.

Abstract: Methods and apparatus for increasing the number of addressable node ports within one arbitrated loop are provided in a way that allows all node ports be able to participate in loop operations. The method also adds destination filtering based on the source address to determine which of the similarly addressed node ports a message is destined for. A unique arbitrated loop physical address is acquired by a connectivity device. A shared arbitrated loop physical address is acquired by each drive in a set of drives attached to the connectivity device. The shared arbitrated loop physical address is part of a set of shared arbitrated loop physical addresses that are shared among a plurality of connectivity devices. The drive can be uniquely addressed using a pairing of the shared loop physical address associated with the drive and the unique arbitrated loop physical address associated with the selected connectivity device.

Abstract: A roofing installation device for enabling quick and accurate installation of shingle type roofing. The device includes a generally c-shaped inner portion and correspondingly c-shaped outer portion slidable relative to one another. The inner and outer portions include at least one spring there between in an expansion state such that manual compression allows a user to clamp the device onto a first shingle layer. An adjustable portion is affixed to the inner portion and includes a stop edge to allow placement of a second shingle layer in such a manner to form a predetermined surface exposure of the first shingle layer. The predetermined surface exposure is variable by moving the adjustable portion relative to the inner portion. Such adjustment is accomplished in a quick, manual manner.

Abstract: An apparatus for the attachment of a racehorse to a racing sulky. The apparatus connects the shafts of the sulky to a harness in a manner so as to isolate racehorse motion from the racing sulky. The apparatus includes a ball joint for rotating attachment to the harness and a threaded end for fixed attachment to the sulky shaft. A dampening piston is provided between the ball joint and the sulky shaft to provide shock absorption and thereby isolate horse movement by dampening the running, trotting, pacing, and galloping motions of the horse from the sulky and vice-versa.

Abstract: A system and method are provided to detect an extended error burst in a data interface. An original error burst has a given length prior to or during transmission. Data transmission processing can extend the original error burst beyond its original length to become an extended error burst with an effective length greater than the original error burst length. Such data transmission processing can include: de-interleaving data on a multi-lane data interface; feedback from a Decision Feedback Equalizer (DFE) receiver; and/or block line decoding, such as 8B/10B block line code decoding. An extended error burst detector can include a suitable error detecting code, such as an r-bit cyclic redundancy check (CRC) code developed in relation to known extended error burst patterns, to detect all extended error bursts based on an up to r-bit original error burst. The detector can also detect error bursts that are not extended beyond the original error burst length.

Abstract: A semiconductor device is provided for preventing Latch-up in Silicon Controlled Rectifiers (SCRs) when these SCRs become activated. Embodiments of the invention use a natively doped region having high resistance to separate the NPN transistor from the PNP transistor that form the SCR, and/or to isolate the entire SCR from the injector source in order to prevent latch-up. The high resistance of the natively doped region allows to achieve the separation resistance needed in a smaller space, as compared to the space required to achieve the same separation resistance in a well. Accordingly, the invention provides for more robust and cost effective latch-up prevention devices.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.