Abstract: A method for testing memory cells, and in particular virgin memory cells, in a multilevel memory device having a plurality of memory cells.

Abstract: A bus arbitration system is described which includes an arbitrator for controlling accesses to a memory bus by a plurality of memory users in response to requests made by those memory users. Each memory user reads the address if a current access to memory and generates a same-address-set signal when the address of the last access by that memory user lies in the same set as the address of the current access. The arbitrator holds for each memory user a predetermined number of accesses which are permitted by that memory user during an access span, and, responsive to a request, grants up to that predetermined number of accesses provided that the same-address-set signal is asserted.

Abstract: A mode-locked fiber laser and a fiber amplifier using a single pump laser, the fiber laser using a pump source to generate soliton optical short pulse and the fiber amplifier amplifying the optical short pulse. The mode-locked fiber laser and fiber amplifier use a single pump laser in accordance with an embodiment of the present invention that includes a tunable directional coupler, a mode-locked fiber laser, and an optical amplifier. The tunable directional coupler is connected to the pump source. The mode-locked fiber laser receives the pump output of the pump source and generates a soliton optical pulse. The mode-locked fiber laser is connected to an output port of the tunable directional coupler. The optical amplifier receives the pump output of the pump source, receives the soliton optical pulse generated by the mode-locked fiber laser, and amplifies the soliton optical pulse. The optical amplifier is connected to the other output port of the tunable directional coupler.

Abstract: A process for the manufacture of a non-volatile memory with memory cells arranged in word lines and columns in a matrix structure, with source lines extending parallel and intercalate to said lines, said source lines formed by active regions intercalated to field oxide zones, said process comprising steps for the definition of active areas of said columns of said matrix of non-volatile memory cells and the definition of said field oxide zones, subsequent steps for the definition of the lines of said matrix of non-volatile memory cells, and a following step for the definition of said source lines.

Abstract: A control or adjusting circuit for a load, a desired signal is compared to an actual signal corresponding to the state of the load, and a PWM control signal is generated in a control signal generating circuit in accordance with the comparison result. The control signal opens and closes a current switch coupled to the load. For forming the PWM control signal, the contents of a ramp counter are compared to the contents of an up/down counter by means of a digital comparator. To obtain fast approximation of the two signals to each other in the case of strong deviations between the desired signal and the actual signal, the up/down counter is subjected to relatively rapid counting in case of high control deviations as compared to low control deviations. To this end, the up/down counter is operated with a clock signal of variable frequency that is produced by a voltage-controlled oscillator as a function of the difference between the desired signal and the actual signal.

Abstract: The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substantially parallel to the first opening and having a second width smaller than the first width is formed on the screening layer. The wafer is then subjected to ion implantation with two ion beams directed in directions substantially perpendicular to the longitudinal axes of the openings and inclined to the surface of the wafer at predetermined angles so as to strike the openings from two opposite sides. The thickness of the screening layer, the widths of the openings, and the angles of inclination of the ion beams being selected in a manner such that the beams strike the base of the first opening for substantially uniform doping of the underlying area of the wafer, but do not strike the base of the second opening.

Abstract: A protective holder for storing and displaying articles, such as photographs, baseball cards, game cards, and the like. The holder is formed from a front sheet that is welded to a back sheet to form a plurality of pockets. Cuts are made in the back sheet to create flaps with tabs that facilitate lifting of the flap for insertion and removal of articles in a manner that minimizes contact damage between the articles and the holder. The flaps are coplanar with the back sheet at all times to prevent indentation of the stored articles when pressure is applied to the flaps. This also enables insertion of entire holder into a thicker, stiffer sheath for further protection, if desired, without the problem of objects dislodging and falling out in the thicker, stiffer sheath.

Abstract: A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas, LV gate regions on second areas of a substrate, and undefined regions on the first and third areas of the substrate; forming first cell source regions laterally to the floating gate regions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining HV gate regions on the third areas, and selection gate regions on the first areas; forming source regions laterally to the selection gate regions, and source and drain regions laterally to the HV gate regions.

Abstract: A circuit arrangement which, in accordance with its mode of control, operates either as input circuit or as output circuit and includes a series connection with an inverter stage, a filter stage, a cross-current avoiding stage, a switching-on voltage reducing stage, a switch stage, an output driver stage, and a Miller feedback stage, which are configured in the mode of operation as an output circuit, and parallel thereto a Schmitt trigger and an analog switch that can become effective in the mode of operation as input circuit.

Abstract: A strap attachment system having a stiffened flexible strap with a first end anchored to a pouch and a free end configured for positioning around a belt and releasable attachment to the pouch, such as with hook-and-loop fasteners. The stiffened flexible strap is formed from webbing that has the hook portion of the hook-and-loop fastening system attached thereto, preferably by stitching. A stiffener having a shaped end is positioned between the hook portion and the webbing to provide some rigidity to the webbing. The stiffened flexible strap is more easily threaded around a belt to form a connecting loop.

Abstract: An amplifier stage having a first and a second transistor connected in series to each other between a first and a second reference potential line. The first transistor has a control terminal connected to an input of the amplifier stage through a first inductor, a first terminal connected to the second reference potential line through a second inductor, and a third terminal connected to a first terminal of the second transistor. The second transistor has a second terminal forming an output of the amplifier stage, and connected to the first reference potential line through a load resistor. To improve the noise figure, a matching capacitor is connected between the control terminal and the first terminal of the first transistor.

Abstract: An evaporated fuel leak detection apparatus for an internal combustion engine that has a fuel tank, a canister with an opening to the atmosphere, a charging passage that causes the fuel tank to communicate with the canister, a pressure adjustment valve installed in the charging passage, an internal pressure sensor installed on the upstream side of the pressure adjustment valve to detect the internal pressure of the fuel tank, and a controller that detects leakage in the fuel tank system on the upstream side of the pressure adjustment valve in accordance with the output of the internal pressure sensor. The controller judges that there is no leakage in cases where the internal pressure sensor indicates a negative pressure, and the vehicle is not in a high-load operating state or when variation in atmospheric pressure is less than a predetermined amount.

Abstract: A manufacturing process providing a zener diode formed in an N-type well housing a first N-type conductive region and having a doping level higher than the well, and a second P-type conductive region arranged contiguous to the first conductive region. The first conductive region is connected, through a third N-type conductive region having the same doping level as the first conductive region, to a conductive material layer overlying the gate oxide layer to be protected. The third conductive region, the well, and the substrate form an N+/N/P diode that protects the gate oxide layer during manufacture of the integrated device from the deposition of the polycrystalline silicon layer that forms the gate regions of the MOS elements.

Abstract: An integrated electronic device having a first charge pump, intended to drive a first line having a high capacitive load, and a second charge pump having a high current pumping capacity and intended to drive a second line, a controlled switch is interposed between the outputs of the two pumps, such as to connect the output of the high current capacity pump to the first line, to charge the first line quickly to the preset voltage, without the first charge pump being oversized. When the voltage present on the first line becomes greater than the voltage at the output of the second charge pump, owing to the current required by the second line, the switch is opened. A common phase generator which drives both the pumps is also provided.

Abstract: A method of forming source and drain regions for LV transistors that includes the steps of forming sacrificial spacers laterally to LV gate regions; forming LV source and drain regions in a self-aligned manner with the sacrificial spacers; removing the sacrificial spacers; forming HV gate regions of HV transistors; forming gate regions of selection transistors; forming control gate regions of memory transistors; simultaneously forming LDD regions self-aligned with the LV gate regions, HV source and drain regions self-aligned with the HV gate regions, source and drain regions self-aligned with the selection gate region and floating gate region; depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask; anisotropically etching the dielectric layer, to form permanent spacers laterally to the LV gate regions; removing the protection silicide mask; and forming silicide regions on the LV source and drain regions and on the LV gate regions.

Abstract: The present invention provides a tunable optical filtering system using fiber-optic polarimetric interferometer. The tunable optical filtering system using fiber-optic polarimetric interferometer in accordance with the present invention comprises a stabilization light source, a first polarization beam splitter, a first optical fiber node, a number of polarization maintaining optical fibers, a phase modulator, a stabilization electronics, a second optical fiber node, a second polarization beam splitter, and two wavelength division optical multiplexers. The stabilization light source supplies stabilization light. The first polarization beam splitter polarizes the stabilization light and the input light to be filtered and generates polarized light. The first optical fiber node connects the output of the first polarization beam splitter with polarization maintaining fibers with the angle of 45 degree between their birefringent axes and splits the polarized light.

Abstract: An electric circuit configuration for shaping the slew rate of a pulsed output voltage occurring at an output terminal and for detecting a short circuit at the output terminal, having: a switchover control circuit for controlling the slew rate of the output voltage as a function of a voltage curve occurring across an internal resistor in a first switching state, and for feedback-controlling the slew rate as a function of the output voltage curve in a second switching state, and which is in a substantially dead state in a third switching state; a detector circuit which provides a detection signal when the output voltage differs by at least a predetermined value from the output voltage level occurring before edge onset; and a timer circuit for switching the control circuit from the first to the second switching state a predetermined length of time after edge onset if the detection signal is present at this time, and from the first to the third switching state if the detection signal is not present at this time.

Abstract: An integrated power operational amplifier can alternatively be operated in a master or a slave mode, such that a master amplifier can be connected in parallel with one or more slave amplifiers. This arrangement allows very low impedance loads to be driven, as well as allowing the heat dissipation to be distributed over a number of operational amplifiers, thereby raising the maximum dissipation limits of integrated power systems. In addition by eliminating the ballast resistors, more power can be delivered by the system, for the same supply voltage, and less power is dissipated.

Abstract: A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.

Abstract: A circuit for the regulation of the word line voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when the one or more word lines are being selected. The circuit includes a voltage boosting circuit that is coupled to the output of said voltage regulator and that can be activated upon the selection of one or more memory word lines in order to boost the regulated voltage upon the selection of the one or more memory word lines.