Abstract: A circuit for providing a reference voltage, including a first transistor of bipolar type, the emitter of which provides the reference voltage and the collector of which is connected to a first supply pole, a second MOS-type transistor, the drain of which is connected to the base of the first transistor and the source of which is connected to a second supply pole, a control block, an output of which is connected to the gate of the second transistor and an input of which is connected to the emitter of the first transistor, a capacitor connected to the output of the control block and coupled to the first supply pole via a first impedance, and a second impedance connected on the one hand to the second transistor and on the other hand to the connection point between the capacitor and the first impedance.

Abstract: The load pump booster device with transfer and recovery of the charge including a charge pump circuit with an output terminal connected to a load capacitor by means of a load node. In turn, the charge pump circuit includes a plurality of transfer transistors connected to one another in series, and define a plurality of transfer nodes. Each transfer node is connected to a storage capacitor. The booster device also includes a plurality of controlled switches interposed between the load node and a respective transfer node, in order to connect to the load node a single one of the transfer nodes. By this means, between the load capacitor and the storage capacitors there takes place a phase of transfer of charge followed by a phase of recovery of charge, from the storage capacitors to the load capacitor. FIG. 1.

Abstract: A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first polysilicon layer over the first gate oxide layer, selectively etching and removing the first polysilicon layer in order to define the floating gate of the memory cell, introducing dopant in order to obtain source and drain regions of the memory cell, depositing a dielectric layer, selectively etching and removing the dielectric layer and the first polysilicon layer in a region wherein the logic transistor will be formed, depositing a second polysilicon layer, selectively etching and removing the second polysilicon layer in order to define the gate of the logic transistor and the control gate of the memory cell.

Abstract: A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas, LV gate regions on second areas of a substrate, and undefined regions on the first and third areas of the substrate; forming first cell source regions laterally to the floating gate regions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining HV gate regions on the third areas, and selection gate regions on the first areas; forming source regions laterally to the selection gate regions, and source and drain regions laterally to the HV gate regions.

Abstract: A process for assembling a microactuator on a R/W transducer that includes forming a first wafer of semiconductor material having a plurality of microactuators including suspended regions and fixed regions separated from each other by first trenches; forming a second wafer of semiconductor material comprising blocking regions connecting mobile and fixed intermediate regions separated from each other by second trenches; bonding the two wafers so as to form a composite wafer wherein the suspended regions of the first wafer are connected to the mobile intermediate regions of the second wafer, and the fixed regions of the first wafer are connected to the fixed intermediate regions of the second wafer; cutting the composite wafer into a plurality of units; fixing the mobile intermediate region of each unit to a respective R/W transducer; and removing the blocking regions. The blocking regions are made of silicon oxide, and the intermediate regions are made of polycrystalline silicon.

Abstract: An integrated circuit provides for a connection port having a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, and a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins. The test access port controller is connectable to the test logic in a first mode of operation to effect communication of serial test data under control of an incoming clock signal and is operable in a second mode of operation to communication data as a sequence of serial bits according to a predetermined protocol between the connection port and the on-chip functional circuitry. The integrated circuit includes an error detection circuit for detecting an error condition in the protocol and gating circuitry responsive to detection of the error condition to prevent communication of subsequent data until the error condition is detected as having been removed.

Abstract: A process of forming on a monocrystalline-silicon body an etching-aid region of polycrystalline silicon; forming, on the etching-aid region a nucleus region of polycrystalline silicon surrounded by a protective structure having an opening extending as far as the etching-aid region; TMAH-etching the etching-aid region and the monocrystalline body to form a tub-shaped cavity; removing the top layer of the protective structure; and growing an epitaxial layer on the monocrystalline body and the nucleus region. The epitaxial layer, of monocrystalline type on the monocrystalline body and of polycrystalline type on the nucleus region, closes upwardly the etching opening, and the cavity is thus completely embedded in the resulting wafer.

Abstract: An inertial sensor having an inner stator and an outer rotor that are electrostatically coupled together by mobile sensor arms and fixed sensor arms. The rotor is connected to a calibration microactuator comprising four sets of actuator elements arranged one for each quadrant of the inertial sensor. There are two actuators making up each set. The actuators are identical to each other, are angularly equidistant, and each comprises a mobile actuator arm connected to the rotor and bearing a plurality of mobile actuator electrodes, and a pair of fixed actuator arms which are set on opposite sides with respect to the corresponding mobile actuator arm and bear a plurality of fixed actuator electrodes. The mobile actuator electrodes and fixed actuator electrodes are connected to a driving unit which biases them so as to cause a preset motion of the rotor, the motion being detected by a sensing unit connected to the fixed sensor arms.

Abstract: The memory device comprises a memory array having an organization of the type comprising global word lines and local word lines, a global row decoder addressing the global word lines, a local row decoder addressing the local word lines, a global power supply stage supplying the global row decoder, and a local power supply stage supplying the local row decoder.

Abstract: An error processing circuit for a receiving location of a system for transferring binary data in the form of pulse sequences, wherein the system has a number of receiving locations connected via a double-line bus having a first line and a second line. The circuit includes a data output, a decoder having three decoder outputs, of which a first decoder output associated with both lines delivers a first decoder output signal dependent on the difference between the potential values of both lines, a second decoder output associated with the first line delivers a second decoder output signal dependent on the difference between the potential value of the first line and a first mean potential value, and a third decoder output associated with the second line delivers a third decoder output signal dependent on the difference between the potential value of the second line and a second mean potential value.

Abstract: A DC-DC converter having a current error amplifier and a voltage error amplifier connected in parallel to control the charging of the battery and a gradual turning off circuit for turning off gradually the current error amplifier in a battery charging end phase. In this way, the DC-DC converter is able to supply to the battery a battery charging current that remains constant until the battery full charge voltage is reached.

Abstract: A memory circuit having a first and a second block of memory cells with rows that cross both blocks and columns in each of the two blocks. A word decoder selects one of the rows, and a column decoder selects a set of columns from the first and second blocks. An address splitter passes relative portions of an address to each decoder. In one embodiment, the address splitter passes the most significant bits of the address to the word decoder and passes the remaining bits to a portion of the column decoder coupled to the first block only. The address splitter also modifies the remaining bits, using a bit subtractor, and passes them to a portion of the column decoder coupled to the second block only. A method of operating a memory device is provided that includes accepting an address at an input address circuit and then determining whether the address is for data in the first block or in the second block. This information is assessed by comparing it to the number of memory cells in the first block.

Abstract: An amplifier circuit including at least one first input amplifier; at least one second amplifier cascode-assembled with the first amplifier; and at least one reactive impedance circuit, mounted in series with the second amplifier, the reactive impedance circuit being formed by two impedances respectively exhibiting a maximum value for a first and a second frequency, to form a double-band amplifier circuit.

Abstract: A keyfact-based text retrieval method and a keyfact-based text index method that describes the formalized concept of a document by a pair comprising an object that is the head and a property that is the modifier and uses the information described by the pairs as index information for efficient document retrieval. A keyfact-based text retrieval system includes keyfact extracting, keyfact indexing, and keyfact retrieving. The keyfact extracting analyzes a document collection and a query and extracts keywords and keyfacts. The keywords do not have part-of-speech ambiguity and the keyfacts are extracted from the keywords. The keyfact indexing calculates the frequency of the keyfacts and generates a keyfact list of the document collection for a keyfact index structure. The keyfact retrieving receive a keyfact of the query and keyfacts of the document collection and defines a keyfact-based retrieval model in consideration of a weight factor of the keyfact pattern and generates a retrieval result.

Abstract: A process for manufacturing a SOI wafer with buried oxide regions without cusps that includes forming, in a wafer of monocrystalline semiconductor material, trenches extending between, and delimiting laterally, protruding regions; forming masking regions, implanted with nitrogen ions, the masking regions surrounding completely the tips of the protruding regions; and forming retarding regions on the bottom of the trenches, wherein nitrogen is implanted at a lower dose than the masking regions. A thermal oxidation is then carried out and starts at the bottom portion of the protruding regions and then proceeds downwards; thereby, a continuous region of buried oxide is formed and is overlaid by non-oxidized regions corresponding to the tips of the protruding regions and forming nucleus regions for a subsequent epitaxial growth.

Abstract: A method of and a circuit arrangement for data transfer between a master means and slave means, in which bit sequences are transferred each having an address field for addressing the respective slave means to be controlled, a control field for control information, and a data field. The data bit number of the data field may be different depending on the addressed slave means. The bit sequences transmitted from the master means are read back directly to the master means, so that the occurrence of corrupt bits in the bit sequence is recognized and a transfer of the bit sequence recognized as corrupt to the addressed slave means can be prevented.

Abstract: A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal.

Abstract: An OTP memory integrated circuit in CMOS technology, including at least two oxide capacitors forming a differential reading storage element, and a read and programming circuit in which the transistors of a first conductivity type are adapted to being used both during read cycles under a relatively low voltage and during programming cycles under a relatively high voltage.

Abstract: The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a layer of silicide on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining stack gate regions and HV gate regions of high-voltage transistors; and forming HV source and drain regions and cell regions.

Abstract: A manufacturing process including: forming a first insulating region on top of an active area; forming a tunnel region at the side of the first insulating region; depositing and defining a semiconductor material layer using a floating gate mask to form a floating gate region. The floating gate mask has an opening with an internal delimiting side extending at a preset distant from a corresponding outer delimiting side of the mask, so that the floating gate region forms inner a hole, and the tunnel region is defined, as regards its length, by the floating gate ask alone. The hole is filled with a dielectric material layer. The surface of the floating gate region is planarized, and an insulating region of dielectric material is made. A control gate region and conductive regions in the active area are then formed.