Abstract: Circuit for the regulation of the word line voltage in a memory, including a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when said one or more word lines are being selected, and charge accumulation means that are selectively connectable with the output of the voltage regulator and suitable to accumulate a compensation charge for a voltage drop that takes place on said regulated voltage upon the selection of said one or more word lines of the memory.

Abstract: A CMOS high frequency variable gain amplifier with maximum high frequency operation and wide variable gain characteristics that is formed from an amplifier having a plurality of variable gain amplifier cells connected in series for continuously enabling wide gain variation; and a control voltage generator for generating and outputting the control voltage of the variable gain amplifier cells. By using both the saturation region and the linear region of input differential transistors constituting the variable gain amplifier cells in order to obtain wide gain variation characteristics, it is possible for the variable gain amplifier to operate in the saturation region when the input signal is small to obtain a high gain and to operate in the linear region when the input signal is large to obtain minimum distortion and a low gain. Also, it is possible for the gain to have the characteristics in the form of an exponential function to the gain control voltage.

Abstract: A process for forming insulating structures for integrated circuits that includes depositing a silicon oxide layer; shaping the silicon oxide layer to form first delimiting walls of the insulating regions substantially perpendicular to the substrate; and shaping the silicon oxide layer to form second delimiting walls inclined with respect to the substrate. The first walls have an angle of between approximately 70° and 110° with respect to the surface of the substrate; the second walls have an angle of between approximately 30° and 70° with respect to the surface of the substrate 11. The first delimiting walls are formed using a first mask and etching anisotropically first portions of the oxide layer; the second delimiting walls are formed using a second mask and carrying out a damage implantation for damaging second portions of the oxide layer and subsequently wet etching the damaged portions.

Abstract: The present invention provides a demultiplexer for generating a constant four-wave-mixing beam without regard to an input polarization state using a dispersion-shifted fiber that is a nonlinear material with high refractive index. A number of parts in conventional demultiplexer implementations, which are sensitive to input polarization state has been replaced with optical fibers of high polarization mode dispersion.

Abstract: A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining salicided HV gate regions of high voltage transistors; and forming HV source and drain regions not directly overlaid by silicide portions.

Abstract: Circuitry is described for transferring information from a first timing environment to a second timing environment. The circuitry comprises a dual port RAM having a first port which is responsive to a first timing signal and a second port which is responsive to a second timing signal, a first control circuit which is responsive to the first timing signal, for controlling storage of data in the dual port RAM through the first port and for generating a control signal indicating that data is stored in the dual port RAM. The circuitry also comprises a synchronizer for synchronizing the control signal to the second timing signal, and a second control circuit, which is responsive to the second timing signal and the synchronized control signal and is for controlling retrieval of stored data through the second port of the dual port RAM.

Abstract: A circuit for detecting the disappearing of a periodic input signal, the circuit including a frequency divider receiving the input signal, the frequency divider having two complementary outputs combined with a same reference signal of same frequency as the input signal by means of two respective similar logic gates, the output of a first one of the logic gates being connected to increment a first counter and to reset a second counter similar to the first one, and the output of the second logic gate being connected to increment the second counter and to reset the first counter, and a logic circuit generating a disappearing detection signal when any one of the two counters reaches a predetermined value.

Abstract: A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations having a differential input stage biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors.

Abstract: An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input receiving a disabling signal, and an output generating an equalization control signal. An auxiliary line is supplied at one initial terminal (35a) with a biasing voltage correlated to the reading voltage supplied to the addressed array cell. An equalization filter is connected to the end terminal of the auxiliary line and generates the disabling signal when the voltage at the end terminal of the auxiliary line exceeds a preset threshold value.

Abstract: An EEPROM cell with improved current performance, the EEPROM cell having: a selection transistor with a drain region, a source region and a control gate, a memory cell having a drain region, a source region, a control gate and a floating gate, the drain region of the memory cell and said source region of the selection transistor are connected together, and the source and drain regions of the memory cell and the source and drain regions of the selection transistor share an active area with a pair of sides that linearly converge from one end to the other end

Abstract: A method of testing a DMOS power transistor that includes arranging a switch between low-voltage circuitry and the gate terminal of the DMOS power transistor, maintaining the switch in an open condition, applying a stress voltage to the gate terminal, testing the functionality of the DMOS power transistor, and, if the test has a positive outcome, short-circuiting the switch through zapping by fusing a normally-open fusible link. An integrated circuit device with DMOS transistor is provided that includes a gate terminal of the DMOS transistor coupled to a control element, a normally-open switch element coupled in series between the gate terminal and the control element and including two metallic regions with an insulating between them connected in parallel with the switch element and in series between the gate terminal and the control element.

Abstract: A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.

Abstract: The method described comprises the following steps: measuring, with a spectroscopic ellipsometer, the values of two quantities which are dependent on the thickness of the altered silicon layer and of a thin layer of silicon dioxide grown thereon with variations in the wavelength of the light of the measurement beam of the ellipsometer, obtaining from these measured values respective experimental curves representing the two quantities as functions of the wavelength, calculating the theoretical curves of the two quantities as functions of the wavelength considering the refractive indices and absorption coefficients of silicon dioxide and of the altered silicon as known parameters and the thickness of the altered silicon layer and the thickness of the thin silicon dioxide layer as unknowns, comparing the theoretical curves with the respective experimental curves in order to determine for which values of the unknowns the curves under comparison approximate to one another best, and extracting from the values dete

Abstract: An evaporated fuel treatment apparatus that includes a fuel tank, a canister with an opening to the atmosphere, a charging passage that causes the fuel tank to communicate with the canister, a purging passage that causes the canister to communicate with the intake manifold of the internal combustion engine, a pressure adjustment valve installed in the charging passage, a bypass valve installed in a passage that bypasses the pressure adjustment valve, a purge control valve installed in the purging passage, a vent shut valve capable of opening and closing the opening port, an internal pressure sensor for detecting the internal pressure of the fuel tank, and a controller that opens the fuel tank to atmospheric pressure or opens the fuel tank to a negative pressure by controlling the bypass valve, purge control valve, and vent shut valve.

Abstract: A device including an IGBT a formed on a chip of silicon consisting of a P type substrate with an N type epitaxial layer that contains a first P type region and a termination structure, and having a first P type termination region that surrounds the first region, a first electrode in contact with the first termination region, and a second electrode shaped in the form of a frame close to the edge of the chip and connected to a third electrode in contact with the bottom of the chip. A fourth electrode made in one piece with the first electrode is in contact with the first region. The termination structure also comprises a fifth electrode in contact with the epitaxial layer along a path parallel to the edge of the first termination region and connected to the second electrode and a second P type termination region that surrounds the fifth electrode and a sixth electrode, and which is in contact with the second termination region, connected to the first electrode.

Abstract: A dual supply device having a reference terminal, an input terminal for the application of a substantially constant input voltage relative to the reference terminal, a first output terminal for supplying a first supply voltage different from the input voltage, a second output terminal for supplying a second supply voltage substantially opposite to the first supply voltage a direct-current/direct-current converter connected between the input terminal and the first output terminal for converting the input voltage into the first supply voltage, and a capacitive translator connected between the first and second output terminals for translating the first supply voltage into the second supply voltage.

Abstract: In an evaporated fuel treatment device for an internal combustion engine which has a fuel tank, a canister having an interior and an opening that opens the interior to the atmosphere, and which adsorbs evaporated fuel generated inside the fuel tank, a charging passage that communicates with the fuel tank and with the canister, a pressure adjustment valve provided in the charging passage, an internal pressure sensor provided upstream from the pressure adjustment valve to detect and output the vapor pressure inside the fuel tank, and a fuel tank system leakage detector that detects leakage in the fuel tank system on the upstream side of the pressure adjustment valve according to the output of the sensor, the device having at least a first stored reference value for a first leak diameter constituting an object of detection and a second stored reference value for a second leak diameter constituting an object of detection, and the leakage detector configured to detect the presence or absence of leakage by comparin

Abstract: A breakaway bracket assembly (10) for connecting two structural members, such as a sign post (12) and a base (14). The bracket (10) has a first end strap (20) configured for attachment to the post (12) and a second end strap (22) configured for attachment to the base (14). The first and second end straps (20, 22) are integrally formed with a central section (24) that comprises a pair of flanges (28, 30) having a preformed brake point (34) that will fail when the first and second end straps (20, 22) are subjected to a predetermined load.

Abstract: A one-time programmable cell including an inverter providing a logic state according to the state of the cell; a fuse coupled between a first supply voltage and the inverter input; and a current source coupled between the fuse and a second supply voltage. The inverter is supplied from the second supply voltage through a first diode-connected transistor and the current source is formed of a second transistor controlled by the inverter output, this second transistor having a threshold voltage greater than that of the first transistor.

Abstract: A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.