Abstract: A digital-analog converter having a sigma delta cascade modulator with two outputs, particularly a third order sigma delta modulator 2+1. The digital-analog converter includes a sigma delta modulator of the type having two outputs able to supply a first and a second signal to the two outputs; a reconstruction circuit of the first and second signals able to provide a reconstructed signal; a filter able to filter the reconstructed signal; the reconstruction circuit combining the first and second signals according to the following relationship: Yout Y1*(1+Z−1)−Y2*(1−Z−1)+Y2*Z−2*(1−Z−1), where: Yout corresponds to said reconstructed signal, Y1 corresponds to said first signal, Y2 corresponds to said according to signal, Z corresponds to the Z transform.

Abstract: A method of signal compression of a signal to reduce the large dynamic range, for example, of the output signal of a CD player in such a way that soft passages of a piece of music are reproduced in somewhat louder manner and very loud passages of a piece of music some are reproduced in somewhat less loud manner. The signal compression circuit used therefor can be integrated completely. The audio signal is fed over a volume control, which can be adjusted by the user, and to this end, a digital setting signal in accordance with the adjustment made on the user side, is supplied via a bus line. When the audio signal is strongly increasing, a tracking signal is formed of said signal, with the amplitude thereof being dependent on the medium amplitude of the audio signal. A window comparator compares the tracking signal with a reference value, as a consequence of which the contents of the up/down counter are reduced. This reduced value is added via an adder to the digital setting signal for the volume control.

Abstract: A PWM power amplifier having at least one PCM/PWM converter fed by PCM digital input signals and producing PWM digital output signals, and at least one power amplification final stage of the PWM digital output signals. At least one PCM/PWM converterincludes a counter fed with at least one clock signal produced by a clock generator device and having a digital comparator suitable for comparing the PCM digital input signals of at least one PCM/PWM converter with a digital comparison signal produced by the counter and producing in output the PWM digital signals. The clock generator device includes a pulse generator device and an oscillator; the pulse generator device receives a signal at a frequency that is equal to the frequency of the PCM digital input signals of the at least one PCM/PWM converter and produces in output reset pulses. The reset pulses are sent in input to the oscillator, which produces in output the at least one clock signal.

Abstract: An A.C./D.C. converter including a filtering capacitor and further including a first branch essentially including a first rectifying circuit and a current limiting circuit; a second branch essentially including a second rectifying circuit, the series voltage drop of which is limited to that of the switches forming it; and a selection circuit for selecting one of the two rectifying circuits.

Abstract: A monocrystalline silicon substrate is subjected to the following operations: implantation of doping impurities in a high concentration to form a planar region of a first type; selective anisotropic etching in order to hollow out trenches to a depth greater than the depth of the planar region; oxidation of the silicon inside the trenches, starting a certain distance from the surface of the substrate, until a silicon dioxide plaque is formed, surmounted by residues of strongly-doped silicon; epitaxial growth between and on top of the silicon residues to close the trenches and to bring about a redistribution of the doping impurities into the silicon grown to produce a buried region with low resistivity in an epitaxial layer of high resistivity.

Abstract: A voltage boosting device having a charge pump circuit formed by a plurality of voltage boosting stages cascade-connected together.

Abstract: Circuitry for adding a first binary number (A) having a plurality of bits (a0, a1, . . . ) to a second binary number (B) having a plurality of bits (b0, b1, . . . ) to produce a third binary number (A+B) having a plurality of bits (s0, s1, . . . ) and/or a fourth binary number (A+B+1) having a plurality of bits (s0′, s1′, . . . ) and corresponding to the addition of the third binary number and one.

Abstract: A method for digital-to-analog conversion of a digital input code into a first output analog signal and a second output analog signal to be supplied to a first terminal and a second terminal, respectively, of an audio load, the conversion being performed by means of a DAC with N-level balanced output, the conversion method includes using N/2 positive generator elements supplying respective positive elementary contributions which are nominally equal to one another, and N/2 negative generator elements supplying respective negative elementary contributions which are nominally equal to one another and, in absolute value, equal to the positive elementary contributions; attributing the same progressive addresses to the positive generator elements and to the negative generator elements; defining a first index for the positive input codes and a second index for the negative input codes; and, in the presence of an input code at the input of the DAC, selecting between the first index and the second index, the index cor

Abstract: An electrical resistor integrated in an integrated semiconductor circuit to have a useful resistor with two spaced-apart useful resistor terminal contact regions and a useful resistor region of semiconductor material located therebetween; and an auxiliary resistor having two spaced-apart auxiliary resistor terminal contact regions and an auxiliary resistor region located therebetween.

Abstract: A switched capacitor low-pass filter incorporates a plurality of integrator stages cascade connected together. The filter includes at least one stage that includes a circuit device for cancelling out glitch pulses. This device is a deglitching circuit provided within the filter. Preferably, each stage in the filter is formed of a deglitching device which acts as a smoothing integrator.

Abstract: An infrared detector device having a PN junction formed by a first semiconductor material region doped with rare earth ions and by a second semiconductor material region of opposite doping type. The detector device comprises a waveguide formed by a projecting structure extending on a substrate, including a reflecting layer and laterally delimited by a protection and containment oxide region. At least one portion of the waveguide is formed by the PN junction and has an end fed with light to be detected. The detector device has electrodes disposed laterally to and on the waveguide to enable efficient gathering of charge carriers generated by photoconversion.

Abstract: A low-noise quadrature phase I-Q modulator having a pair of Gilbert cell input stages driven by a feed voltage line and receiving in input respective square wave command signals coming from a local oscillator. The modulator comprises a transistor block with transistors connected to each cell and destined to carry out a voltage-current conversion of a signal in radio frequency received from the block itself; such block further including a single degeneration resistance.

Abstract: A voltage boosting device for speeding power-up of multilevel nonvolatile memories, including a voltage regulator and a charge pump and having an output terminal; the voltage regulator having a regulation terminal connected to the output terminal, and an output supplying a control voltage; the read charge pump having an output connected to the output terminal and supplying a read voltage. The device further includes an enable circuit connected to the output and having a pump enable output connected to a charge pump enable terminal and supplying a pump enable signal. The pump enable signal is set at a first logic level so as to activate the charge pump when the read voltage is lower than a nominal value. In addition, the device generates a power-up sync signal which activates a read operation when the read voltage reaches its nominal value and a chip enable signal is set at an active value.

Abstract: A CMOS technology voltage booster having plurality of charge-pump stages cascade connected together and driven by a plurality of phases, each stage having a terminating input node and a terminating output node, with at least one transistor connected therebetween that has its control terminal connected to an internal circuit node of the same stage and applied one of the phases. This voltage booster further includes a pair of additional circuit elements for transferring, onto the internal node, a potential exceeding the voltage at the input node by at least one threshold. A first of the additional elements is essentially a MOS transistor having its control terminal connected to the control terminal of that transistor that is connected between the input and the output of the stage, while the second additional element is an auxiliary capacitor having one end connected directly to the first additional element and connected to the internal node through a transistor.

Abstract: An OTP memory cell in CMOS technology, including a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region deeper and less doped than the source.

Abstract: A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining salicided HV gate regions of high voltage transistors; and forming HV source and drain regions not directly overlaid by silicide portions.

Abstract: A slope control device for an electric data transmission system having a first line and a second line for differentially transmitting binary data pulses in such a manner that a first logic value of the data pulses has a high potential on the first line and a low potential on the second line associated therewith and a second logic value of the data pulses has a low potential on the first line and a high potential on the second line associated therewith, said slope control device being designed such that it regulates the slope steepness of the potential curve of a first one of both lines to a desired value; compares the slope steepness of the potential curve on one line to the slope steepness of the potential curve on the other line; and compares the slope steepness of the potential curve of the second line as a function of the comparison result.

Abstract: To increase the facing surface and thus the coupling between the floating gate and control gate regions of a memory cell, the floating gate and control gate regions have a width that is not constant in different section planes parallel to a longitudinal section plane extending through the source and drain regions of the cell. In particular, the width of the floating gate and control gate regions is smallest in the longitudinal section plane and increases linearly in successive parallel section planes moving away from the longitudinal section plane.

Abstract: A switched operational amplifier with fully differential topology, alternately switchable on and off, and a control circuit. The operational amplifier has a first differential output (4a) and a second differential output, and a control terminal. The control circuit includes a capacitive detecting network including a first capacitor and a second capacitor connected between the first and second differential outputs and a common-mode node, and a third capacitor connected between the common-mode node and ground in a first operative condition, and between the common-mode node and the supply voltage in a second operative condition. A control transistor is connected between the common-mode node and the control terminal of the operational amplifier and supplies a control current correlated to the voltage on the common-mode node. A switchable voltage source, connected to the common-mode node, supplies a desired voltage in a first operative condition, when the operational amplifier is off.

Abstract: A sensor with a movable microstructure including a sensitive element, formed in a first chip of semiconductor material for producing an electrical signal dependent on a movement of at least one movable microstructure relative to a surface of the first chip. The sensitive element is enclosed in a hollow hermetic structure, and circuitry for processing the electrical signal is formed in a second chip of semiconductor material. The hollow hermetic structure includes a metal wall disposed on the surface of the first chip around the sensitive element, and the second chip is fixed to the metal wall.