Patents Represented by Attorney, Agent or Law Firm Edward J. Kondracki
  • Patent number: 6521289
    Abstract: A dimensionally stable carpet underlay manufactured from needle-punched fibers arranged to form a non-woven felt fabric, to which an acrylic latex pressure sensitive adhesive is applied by a dipping process that coats the surfaces of the fibers and fills the interstices between the fibers. The acrylic adhesive is applied to the felt substrate in a dip and squeeze operation, which passes a felt web through a trough of adhesive and then through an excess adhesive removal station, after which, a protective releasable polymer film is applied to the exposed adhesive surfaces prior to curing step. The acrylic adhesive is selected to exhibit sufficient tackiness to secure the carpet in place, but allowing for easy removal and not leaving a residue after removal of the carpet from the underlay or removal of the underlay from the underlying supporting floor surface.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: February 18, 2003
    Inventor: Oliver A. Wyman
  • Patent number: 6523056
    Abstract: The invention relates to a process for securely comparing two main storage registers, comprising defining an auxiliary storage register (A), calculating a first sum of the words composing the auxiliary storage register, comparing the words of the two main storage registers, randomly selecting one of the words of the auxiliary storage register, and modifying the value of the selected word by a first predetermined value if said words of the main storage registers are identical, and modifying the value of said selected word by a second predetermined value if said words of the main storage registers are different, calculating a second sum (SA2) of the words of the auxiliary storage register, and modifying the second sum by a value equal to said first value multiplied by the number of words (n) of the main storage registers, and comparing said first and second sums (SA1, SA2). The invention also relates to the associated security module.
    Type: Grant
    Filed: February 11, 2000
    Date of Patent: February 18, 2003
    Assignee: Bull CP8
    Inventors: BenoƮt Bole, Jean-Luc Salles
  • Patent number: 6516040
    Abstract: A process and interface for interconnection of multiprocessor modules by point-to-point serial-to-parallel links. Data processing or data communication modules (A and B) are interconnected by means of high-speed point-to-point serial links conveying multiplexed information organized into frames comprising a start-of-frame recognition pattern. The process, on transmission and on reception, performs an analog synchronization of the basic clocks of the modules to a reference clock generated by one of the modules designated as a reference module, called the master module, the other modules being called slave modules, and a digital synchronization of the start-of-frame of each slave module to the start-of-frame sent by the master module.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: February 4, 2003
    Assignee: Bull, S.A.
    Inventors: Georges Lecourtier, Anne Kaszynski
  • Patent number: 6509074
    Abstract: A dimensionally stable rug underlay manufactured from needle-punched fibers arranged to form a non-woven felt fabric, to which an acrylic latex pressure sensitive adhesive is applied by a dipping process that coats the surfaces of the fibers and fills the interstices between the fibers. The acrylic adhesive is applied to the felt substrate in a dip and squeeze operation, which passes a felt web through a trough of adhesive and then through an excess adhesive removal station, after which, a protective releasable polymer film is applied to the exposed adhesive surfaces prior to curing step. The acrylic adhesive is selected to exhibit sufficient tackiness, while not leaving a residue after removal of the rug underlay from the underlying surface.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: January 21, 2003
    Inventor: Oliver Wyman
  • Patent number: 6505144
    Abstract: Terminal equipped with an application program, with at least one output constituted either by a display, or by a printer, or by a communications network, or by a portable object, and cooperating with a portable object equipped with a non-volatile memory area (ZD) containing data, and comprising a reader which communicates with said portable object, characterized in that the device comprises means for reading or storing, in its memory, self-diagnostic or supervisory data (Ti, Dj, Sk) and means for sending said data to outputs (1-4) specified as a function of information supplied by the self-diagnostic or supervisory data following the execution of at least one task Tt of its application program in connection with the portable object.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: January 7, 2003
    Assignee: BULL CP8
    Inventor: Ronan Lapie
  • Patent number: 6488183
    Abstract: An urging device includes: an urging actuator (7); and an urging mechanism actuatable by the urging actuator in an urging direction for effecting a translational movement of a member (3), the urging mechanism being configured such that, upon actuation thereof, at least a first portion (11a) thereof moves in a first direction, and a second portion thereof moves in a second direction different from the first direction, and a second portion thereof moves in a second direction different from the first direction. Additionally, a dispensing kit (5) implements the above urging device. The dispensing kit comprise a dispensing cartridge (15) which includes a cartridge body. A cartridge actuator (21) is disposed at the head portion of the cartridge body.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: December 3, 2002
    Assignees: Weimer Pharma GmbH, L+N Plast Vertriebs GmnH
    Inventors: Willmar Braeuninger-Weimer, Arnold Neuhold
  • Patent number: 6483920
    Abstract: The present invention relates to a key recovery process used for strong encryption of a message sent by an entity, which message is either to be stored locally or transmitted to another entity, the reading of a message requiring a decryption key which can be reconstructed at least by a trusted third party for key recovery, while added to the message are a compensation field and a compulsory control field which itself comprises at least one key recovery field for allowing at least one trusted third party to supply the decryption keys that enable the encrypted message to be read. This key recovery process is remarkable in that the compulsory control field also comprises, in unencrypted form, the current date as well as the agreement number of the encryption hardware/software and, encrypted under a daily intermediate key, the dialogue key.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: November 19, 2002
    Assignee: Bull, S.A.
    Inventor: Denis Pinkas
  • Patent number: 6484160
    Abstract: The invention relates to a process for optimizing accesses to a database. This process allows client applications to request a CMIS-DB server, via an online configuration, to customize the generic representation for the object classes for which the access times must be optimized in order to reduce the search times for the object instances selected, by performing a step for configuring the physical storage of an object class to be optimized, which consists in the creation of an object instance of the storage definition class (mocStorageDefinition), in which are declared the attribute or attributes of the class to be optimized, which will be indexed when physically stored on a disk.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: November 19, 2002
    Assignee: Bull S.A.
    Inventors: Jean-Luc Richard, Alain Grignac
  • Patent number: 6480900
    Abstract: The invention relates to a communication process via an internet network that comprises distributed systems (S1). Each system (S1) is connected to the network (SRX) via a standard interface module (10), standard software layers (12, 13) comprising a stack of addresses and protocols, and hosts software entities (SVA, SVB). The latter and the systems (S1) are provided with a network address in a virtual subnetwork to which the system itself (S1) and said software entities (SVA, SVB) are connected via a specific interface module (11, 20, 30) and specific software layers (21-22, 31-32) comprising a stack of addresses and protocols. The addresses and names of the systems (S1) and of the software entities (SVA, SVB) connected to the virtual networks (SVNy) are stored in a domain name directory (DNS1), making it possible to directly address one of the software entities (SVA, SVB).
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: November 12, 2002
    Assignee: Bull, S.A.
    Inventor: Michel Habert
  • Patent number: 6480933
    Abstract: A disk cache device for secure writing comprising a backup power supply source (62) for supplying backup power for a given duration to a computer system fed by two main electric power supply devices (60, 61) and comprising at least one hard disk drive (1a, 1b, 1c), and a host system (3). All of the disk drives (1a, 1b, 1c) are linked by a bus (2) to a connection (30) of the host system (3) (host bus adapter), and a monitor (50) for monitoring at least the backup electric power supply source (62) and the main power supply devices (60, 61). Monitors (50) are connected to the interface (2) and can be interrogated by an interrogator (31) for interrogating the host system (3) so that the latter can enable the write disk cache function, or not, in the write commands to be sent to the disk drives (1a, 1b, 1c) in accordance with the information gathered by the monitoring means (50).
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: November 12, 2002
    Assignee: Bull S.A.
    Inventors: Laurent Cargemel, Daniel Carteau, Jacques Delepoulle
  • Patent number: 6477564
    Abstract: The present invention relates to a process for transforming and routing data between agent servers present in some machines and a central agent server present in another machine. The agent server comprises autonomous agents (5) that communicate via notifications, a storage layer and an agent machine comprising an execution engine, a communication channel and two message queues for the notifications, a local queue (mqIn) and an external queue (mqOut). The execution engine takes a notification in the local queue, determines and loads the corresponding agent for each notification, has the agent react to the notification, which agent can then change its status and/or send notifications to the communication channel (2), which stores them in the local queue if they are addressed to a local agent and in the external queue if they are addressed to an agent of another server.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: November 5, 2002
    Assignees: Bull S.A., Inria
    Inventors: Andre Freyssinet, Marc Herrmann, Serge Lacourte
  • Patent number: 6477597
    Abstract: The lock architecture for a computer system comprises several processors (10, 11, 12, 13) such that each processor (10) requesting a resource of the system takes control of said resource if a first lock state indicates that said resource is free. The requesting processor is placed on active standby if a second lock state indicates that said resource is busy. A lock includes a first and second lock state. The first lock state corresponds to a null value, and the second lock state corresponds to a non-null value.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: November 5, 2002
    Assignee: Bull, S.A.
    Inventors: Jean-Dominique Sorace, Nasr-Eddine Walehiane
  • Patent number: 6473607
    Abstract: The present invention provides for a system for operating a communication device (20) for reception of scheduled intermittent information messages (22) with a dual mode timer (70) that extends battery life. A controller (50) schedules the timer (70) to power down all idle components of the device (20) between message receptions in a power saving sleep mode to conserve battery power. During active mode when the device is fully active in reception of messages, the timer (70) uses a reference oscillator (90) with a relatively high frequency to support digital processing by the receiver (26). During sleep mode when only the timer is powered on, a much lower frequency sleep oscillator (96) is used to maintain the lowest possible level of power consumption within the timer itself. The timer (70) has provision for automatic temperature calibration to compensate for timing inaccuracies inherent to the low-power low-frequency crystal oscillator (96) used for the sleep mode.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: October 29, 2002
    Assignee: Broadcom Corporation
    Inventors: Aki Shohara, Emilia Vailun Lei
  • Patent number: 6473848
    Abstract: On a machine with non-uniform memory access distributed over several modules, each module includes one or more processors for executing tasks on a virtual or physical addressing space by effective addresses generating logical page numbers to which it is possible to make physical page numbers correspond in the memory by a correlation tale. The generation of a logical page number causes a first-level page-fault type exception when the logical page number is absent from the correlation table. The method includes a step for activating a function (Trace), following each first-level page-fault type exception, a trace function, which records the value of the effective address that has generated the logical page number that has caused the exception, the date when the exception is caused, an identifier of the task using the effective address, an identifier of the processor executing the task and the physical page number corresponding to the logical page number that has caused the exception.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: October 29, 2002
    Assignee: Bull, S.A.
    Inventors: Nadia Bouraoui, Jean-Pascal Mazzilli
  • Patent number: 6472733
    Abstract: The invention relates to a substrate for an electronic circuit (9), the electronic circuit carrying at least one contact pad, the substrate comprising an insulating element (3, 12) housing the electronic circuit and carrying, on an external side, a conductive layer defining at least one contact region (7, 8), said contact pad being connected to said contact region. The substrate comprises at least one fragile zone (5, 6) disposed in the insulating element (3, 12). The electronic circuit substrate may be constituted by a chip card wherein an external readable button contains the electronic circuit. The chip card may cooperate electrically with a card reader.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: October 29, 2002
    Assignee: Bull CP8
    Inventor: Alain Le Loc'h
  • Patent number: 6470054
    Abstract: The present invention relates to a bidirectional two-way CMOS link of the type including a tailored transmission line (AB) connecting two integrated circuits to its two ends. The integrated circuits respectively including a transceiver that includes a transmitter stage (7; 20) and a receiver stage (10), interfacing with the transmission line (AB) and controlled to transmit or receive digital data exchanged over the transmission line (AB) as a function of a control signal (transmission_gd) to put it in either the transmission mode or the reception mode, the transceivers never being in the same mode at the same time. The link is characterized in that each transceiver includes at least one PMOS transistor (MA), and one (NMOS) transistor (MB), which are controlled respectively by the control signal and are dimensioned and arranged to adapt the link to the two ends of the transmission line (AB). The invention in particular is utilized in tailoring of links that connect processors of a multiprocessor platform.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: October 22, 2002
    Assignee: Bull S.A.
    Inventors: Jean-Marie Boudry, Marcelo Duhalde
  • Patent number: 6463266
    Abstract: The present invention provides for a system and method for improvement of radio transmitter and receiver frequency accuracy for a local radio communication unit that communicates digital data with a remote communication unit. In the local unit the received radio signal is down-converted, and converted to complex baseband digital samples by an analog-to-digital converter. A downlink digital phase rotator applies a fine frequency shift to the samples in accordance with a receiver frequency offset command. The resultant baseband signal is used by the data demodulator and by a receiver frequency error estimator to obtain receiver frequency errors. A data modulator generates baseband complex samples which are shifted in carrier frequency by an integrated uplink digital phase rotator in accordance with a transmitter frequency offset command. The modulated samples are then converted by a digital-to-analog converter and upconverted in frequency for radio transmission to the remote unit.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: October 8, 2002
    Assignee: Broadcom Corporation
    Inventor: Aki Shohara
  • Patent number: 6434679
    Abstract: The invention relates to an architecture for management of vital data in a multi-module digital data processing machine (1) and the process for its implementation. Each module (M1 through Mn) comprises a physical nonvolatile memory (NVM1 through NVMn) in which vital data is stored. A first area (G1 through Gx) stores global vital data obtained by copying and associated with the operation of the machine (1). A second area (L1 through Lx) stores local vital data associated with the operation of the module (M1 through Mn). A virtual nonvolatile memory in two parts, global memory and local memory divided into windows, makes it possible, under the control of an extension of the operating system, to address the physical nonvolatile memories (NVM1 through NVMn). The windows of a defective module (M1 through Mn) are not visible. At the startup, a specific firmware determines the state of the modules (M1 through Mn).
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: August 13, 2002
    Assignee: Bull, S.A.
    Inventors: Marie-Antoinette de Bonis-Hamelin, Zoltan Menyhart
  • Patent number: 6430613
    Abstract: The present invention relates to a process and a system for network and system management. The process for network management comprises at least one submanager (COACH) located in a containing tree between a main manager (AD) and the equipment units of a local area network. The submanager is located in the local area network (RLE) and is managed by the main manager (AD). A subnetwork comprises various modules that communicate with one another and with the main manager (AD) through a kernel (N). The modules poll the equipment of the subnetwork and receive the alarms sent by agents (SNMP) operating in the equipment units of the subnetwork.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: August 6, 2002
    Assignee: Bull, S.A.
    Inventors: Jean Brunet, Florence Lamberet
  • Patent number: 6430686
    Abstract: The present invention relates to a disk storage subsystem with multiple configurable interfaces, characterized in that it comprises at least one interface adapter board (1a, 1b), at least one drawer (4), each comprising a plurality of disks (20), each drawer (4) being connected to an adapter board (1a or 1b) by SCSI disk interfaces (2), a first adapter board (1a or 1b) comprising a switch (11) for modifying the addressing system of the disks (20) of at least one drawer (4), the adapter board or boards (1a, 1b) each comprising two independent single-ended/differential-ended SE/DE converters (7), each SE/DE converter (7) being connected to a drawer (4) and fed by either of two direct current/direct current DC/DC converters (7) of the adapter board (1), and two external SCSI connectors (10) being connected to each SE/DE converter (7).
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: August 6, 2002
    Assignee: Bull, S.A.
    Inventors: Laurent Cargemel, Daniel Carteau, Jacques Delepoulle