Abstract: A system and method for accessing a number of communication lines by one or more testing devices is disclosed. Each of the communications lines is coupled through the system and includes a first termination at a first telecommunications termination site and a second termination at a second telecommunications termination site. The system includes a number of line access devices, each of which is coupled to at least one of the communication lines terminating at the first telecommunications termination site and at least one of the communication lines terminating at the second telecommunications termination site. The system further includes a test device interface, signal direction circuitry, a communications device that facilitates remote access to the test access system by a remote processing unit, and a control device.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to apply erase voltage pulses to the non-volatile memory cells and perform erase verification operations. A pulse counter is coupled to count the erase pulses applied to the non-volatile memory cells. A programmable erase pulse register has been described that indicate a number of initial erase pulses that can be applied to the non-volatile memory cells during an initial verification operation prior to performing a scan operation of the memory block. The control circuitry can also apply additional erase pulses following subsequent erase verification operations. A second programmable erase pulse register is provided to indicate a number of subsequent erase pulses that can be applied to the non-volatile memory cells before performing additional scan operations.

Abstract: A photolithographic mask includes a substrate having a single masking layer from which are formed regions of phase shifting between the substrate and the masking layer and regions of non-phase shifting between the substrate and the masking layer. The photolithographic mask is formed using a single masking layer with binary mask technology in one set of regions and attenuated phase shift lithography in a second set of regions.

Abstract: Memory devices having redundancy selection circuitry are adapted to introduce test input signals into the redundancy selection path. The memory devices include a redundancy selection circuit having a latch for latching an incoming redundancy match signal. The latch includes a pair of reverse-coupled inverters. The latch is further coupled to receive one or more test input signals. The latch is responsive to one or more control signals to selectively generate the latched match signal from the incoming redundancy match signal or one of the test input signals. When the latched match signal is generated from the incoming redundancy match signal, the logic level of the latched match signal is independent of the logic level of any of the test input signals. When the latched match signal is generated from one of the test input signals, the logic level of the latched match signal is independent of the logic level of the incoming redundancy match signal.

Abstract: Memory chips containing multiple-bank memory devices are arranged to be mounted in a memory package with the major axis of the memory chip aligned substantially parallel with the major axis of its memory package. Memory devices of various embodiments contain banks of non-volatile flash memory cells and have access commands synchronized to a system clock. Data chip bond pads for coupling to data pins of a memory package are located in a first quadrant of the memory chip. Address chip bond pads for coupling to address pins of a memory package are located in an opposite quadrant of the memory chip.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The memory automatically provides status data when a read command is received for a memory array location that is currently subject to a write operation. The automatic status output allows multiple processors to access the memory device without substantial bus master overhead. The memory can also output status data in response to a status read command.

Abstract: Floating-gate memory cells having a control gate for coupling to a word line, a floating gate, a first source/drain region for coupling to a bit line, and a floating second source/drain region are adapted for use in flash memory devices. Such floating-gate memory cells eliminate the need to provide electrical contact to the second source/drain region, thus simplifying the fabrication process and array architecture. The floating-gate memory cells may be programmed using band-to-band tunneling. The floating-gate memory cells may be read using capacitance sensing or forward current sensing techniques.

Abstract: A non-volatile memory generates a pump voltage from a voltage source, which is typically a charge pump circuit or alternative source. The memory includes a non-volatile memory array having a plurality of memory cells. The pump voltage is utilized to erase or program the floating gate memory cells. After the non-volatile memory device completes an erase or programming operation, the pump voltage source is disabled. A discharge control circuit gradually discharges all of, or the initial component of, a remaining programming voltage charge to ground. The discharge control circuit, therefore, reduces noise caused by a large discharge current spike in the non-volatile memory device.

Abstract: An integrated circuit output driver has been described. The driver can operate in a mode selected from a group of possible modes. The described driver can operate in either a positive emitter coupled logic (PECL), a current mode logic (CML), a grounded low voltage differential signal (GLVDS), or a low voltage differential signal (LVDS) mode. The driver circuit includes a output driver, an emphasis circuit and termination circuitry. A driver bias circuit controls the bias currents for the output driver and the emphasis circuit. The driver bias circuit is controlled to select the desire driver mode. A termination circuitry can be activated based upon the selected mode.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory includes a clock connection to receive an external clock signal, a chip select (CS#) connection to receive a chip select signal, a row address strobe (RAS#) connection to receive a row address strobe, a column address strobe (CAS#) connection to receive a column address strobe and a write enable (WE#) connection to receive a write enable signal. Control circuitry is provided to perform a burst read operation of memory cells in a first block of the memory and interrupt the burst read operation when the chip select signal is active, the row address strobe is either inactive or active, the column address strobe is de-active, the write enable signal is active, and the address signals identify the first block simultaneously during the burst read operation.

Abstract: An apparatus comprises a protection group. The protection group includes components, a signal bus, including segments and connectors, that couple the components. The components also include a plurality of working components, and a protection component. Each connector is included in a working component. Each segment couples two adjacent components. The signal bus is terminated by the protection component. A method comprises generating a first signal from a plurality of working components. The first signal is analyzed by a protection component to determine if any working component is improperly functioning. The protection component transmits a second signal to the plurality of the working components to turn off an improperly functioning working component. Data signals are routed by coupling the improperly functioning working component through a signal bus to the protection component. The data signals are processed by the protection component.

Abstract: A apparatus for providing a Fast Fourier Transform (FFT) and an inverse FFT is provided. The apparatus comprises a radix-N core. The radix-N core includes at least N multipliers. The radix-N core also includes a twiddle-factor lookup table that stores complex twiddle-factors. The twiddle-factor lookup table is coupled to one input of each of the multipliers. The radix-N core also includes a conversion random access memory (RAM) that stores transform points. The conversion RAM is coupled to another input of each of the multipliers. The radix-N core also includes an array of at least N-times-N adder-subtracter-accumulators.

Abstract: A testing apparatus that comprises an electrical device. A first circuit is in electrical communication with the electrical device. The first circuit including an amplifier. First and second couplers are electrically connected to the first circuit and arranged in series with the amplifier. The amplifier is positioned between the first and second couplers. A second circuit has a first end in electrical communication with the first coupler and a second end in electrical communication with the second coupler. The total gain of the first coupler, the second coupler, the portion of the first circuit between the first and second couplers, and the second circuit is approximately zero.

Abstract: A motor noise silencer reduces noise at a source, such as an unbalanced electromechanical motor. The silencer, in one embodiment, comprises a multi-layer shell and an integrated vibration-based cooling system. The shell has an inner layer, a middle sound and vibration absorbing layer, and an external layer. The middle layer offers a soft coupling between the outer and inner layers. Heat trapped within the silencer is channeled out by utilizing a vibratory motion of a source (i.e., motor) and motor support system. The silencer provides noise reduction while providing ventilation using vibration generated by the motor.

Abstract: A video and telephony signal distribution network is provided. The network includes a head end for transmitting to a plurality of remote units. The network further includes at least one optical/electrical converter unit that transmits to the remote units over at least two coaxial cables coupled to a common optical/electrical converter unit. Each remote unit transmits upstream electrical data signals over its associated coaxial cable to the optical/electrical converter unit using a common bandwidth. The optical/electrical converter unit converts and frequency shifts the upstream electrical data signals from at least one remote unit to form an optical upstream data signal for transmittal to the head end such that the frequency spectrum used for the upstream communications is simultaneously used on each of the coaxial cables of to optical/electrical converter unit.

Abstract: Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a “sub-bit” comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term “sub-bit” means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.

Abstract: A method for initializing a service unit in a communication system. The method includes receiving a synchronization signal from a head end at the remote unit. Further, an identifier is received specifying the remote unit. The method further receives an upstream frequency band and control channel designation at the remote unit, wherein the frequency band includes a number of subbands with at least one control channel in each subband. The method tunes to the designated frequency band and a reference signal is transmitted on a selected channel to the head end. The method receives adjustment signals based on the reference signal transmitted to the head end to allow signals transmitted from the remote unit to be orthogonal at the head end to signals from at least one other remote unit. The method adjusts parameters at the remote unit based on the adjustment signals.

Abstract: A method for controlling gain in a network is provided. The method includes receiving signals for transmission over a network and adjusting the level of the received signals. The method further includes inserting an additional signal indicative of the level adjustment and transmitting the signals and the additional signal over the network. The method also includes extracting the additional signal after transmission over the network and compensating for the level adjustment based on the extracted signal.