Abstract: A method for controlling the data rate of a virtual connection. Data packets are received for transmission on the virtual connection. The method comprises buffering the data packets in a buffer. A counter signal is generated to indicate the beginning of timeslots in a measurement window. The number of timeslots needed to transmit the data packets with a selected data rate is determined. The method further accesses data from at least one table to determine the spacing between timeslots in the measurement window used to request access to a data bus based on the number of timeslots needed to achieve the selected data rate. Further, access to a data bus for the data packets in the buffer is requested based on the data accessed from the table. The method further transmits the packets when access to the bus is granted.

Abstract: A conditioner unit is wired in parallel with a pair gain test controller used to test a digital loop carrier telephone network. The conditioner unit senses a signal intended to request test results from the pair gain test controller and provides a response signal which indicates that the pair gain test controller performed a successful test, even though the pair gain test controller was not activated. This allows testing of the network without use of a bypass pair or the need to interface the digital loop carrier network with the pair gain test controller.

Abstract: A semiconductor device or integrated circuit has high and low resistive contacts. Mobility spoiling species such as carbon or oxygen are implanted into all contacts. The high resistive contacts are covered with a barrier metal to protect silicide from chemical interaction with the interconnect metalization (aluminum) in the low-resistance contacts. Selective silicide formation converts some of the contacts back to low-resistance contacts.

Abstract: Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capacitor. In another embodiment, the top electrode is formed interior to, and exterior and below a portion of the bottom electrode of the container capacitor. The method of forming a top electrode of a container capacitor and a contact plug with a same deposition is particularly well-suited for high-density memory array formation.

Abstract: Memory devices including blocks of memory cells arranged in columns, with each column of memory cells coupled to a main bit line, are organized for high-speed access and tight packing. Such memory devices include sector bit lines having multiple main bit lines selectively coupled to each sector bit line, with each sector bit line extending to main bit lines in each memory block of a memory sector. Sector bit lines are coupled to sensing devices and the output of each sensing device is selectively coupled to a global bit line, with each global bit line selectively coupled to more than one sensing device. The global bit lines are multiplexed and input to helper flip-flops for output to the data output register of the memory device. Various embodiments include non-volatile, and, particularly, synchronous non-volatile memory devices having multiple banks containing multiple sectors of such memory blocks.

Abstract: Undesirable vibrations are controlled in a mechanical structure by confining the vibrations to one or more specified areas of the structure and then dissipating the confined energy by damping. Vibration confinement is achieved using a confinement device which effectively applies both translational and torsional forces to the structure. The strength of the translational and torsional forces, and the position of the confinement device are chosen to select a vibrational energy confinement region. Damping elements are concentrated in the vibration confinement region to dissipate the confined vibrational energy. Judicious selection of the confinement region permits the structure to avoid the transfer of vibrational energy to particularly sensitive portions of the structure, or to direct vibrational energy to a portion of the structure. Optimization procedures are presented for designing structures having optimized placement and selection of the vibration confinement device and damping devices.

Abstract: A method of forming an extraction grid for field emitter tip structures is described. A conductive layer is deposited over an insulative layer formed over the field emitter tip structures. The conductive layer is milled using ion milling. Owing to topographical differences along an exposed surface of the conductive layer, ions strike the exposed surface at various angles of incidence. As etch rate from ion milling is dependent at least in part upon angle of incidence, a selectivity based on varying topography of the exposed surface (“topographic selectivity”) results in non-uniform removal of material thereof. In particular, portions of the conductive layer in near proximity to the field emitter tip structures are removed faster than portions of the conductive layer between emitter tip structures. Thus, portions of the insulative layer in near proximity to the field emitter tip structures may be exposed while leaving intervening portions of the conductive layer for forming the extraction grid.

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.

Abstract: A telecommunications network is provided. The network uses a ring of ring switches to provide a transport mechanism for data packets that is transparent to the data and protocols contained in the data packets. This transport mechanism is simple and low cost to implement. Such networks can carry, for example, data to and from the Internet to a subscriber with a cable modem hook-up to a cable network or a DSL modem connection to a copper wire DSL enabled telephone network.

Abstract: A delay locked loop having improved synchronization times has a variably adjustable delay line which accepts two incoming clock pulses. As each pulse propagates through the delay line an edge of the pulse toggles or retoggles a shift bit corresponding to a delay element. When the first pulse reaches the end of the delay line, the status of the shift bits is frozen, and a starting point for a synchronization sequence begins at the transition point between toggled and retoggled shift bits.

Abstract: A read reference scheme that uses current load matching on a reference word line path. In one embodiment, a flash memory device comprises a word line, a reference word line and a reference load circuit. The word line is coupled to a control gate of a memory cell. The reference word line is coupled to a control gate of a reference memory cell. In addition, the reference load circuit is coupled to the reference word line to approximately match a current load on the word line so a voltage level on the reference word line will be approximately equally to a voltage level on the word line during a read operation.

Abstract: A non-volatile memory device includes an array of erasable blocks of non-volatile memory cells. At least one of the blocks has at least one redundant column. A block register is associated with each erasable block. Each block register stores data that indicates when its associated erasable block is fully erased. A control circuit is used to perform an erase verification on each erasable block and provide data to the block registers based on an outcome of the erase verification. The control circuit performs the erase verification of the at least one redundant column in conjunction with the erasable block where the at least one redundant column resides.

Abstract: Memory devices having architectures permitting the application of a voltage differential across alternate bitlines facilitate identifying and locating shorts within the memory device with particular reference to flash memory devices. The memory devices include a first plurality of selective coupling devices coupled between a first plurality of bitlines and a first variable potential node. The memory devices further include a second plurality of selective coupling devices coupled between a second plurality of bitlines and a second variable potential node. The first plurality of selective coupling devices are responsive to a first control signal to selectively provide electrical communication between the first plurality of bitlines and the first variable potential node. The second plurality of selective coupling devices are responsive to a second control signal to selectively provide electrical communication between the second plurality of bitlines and the second variable potential node.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can detect a brown-out of a supply voltage. The memory device comprises a voltage detection circuit to monitor a supply voltage and provide a signal if the supply voltage drops below a predetermined value. A latch is coupled to the voltage detection circuit and can be programmed to indicate if the supply voltage dropped below the predetermined value. An external controller can read a status of the latch. The memory, therefore, can provide an indication to an external controller that a reset, or initialization, operation is needed.

Abstract: Bi-state ferroelectric-MOS (FMOS) capacitors are adapted for use in memory cells of a memory device. Bi-state ferroelectric memory cells have a bottom plate of a capacitor coupled to a first source/drain region of a pass transistor, a gate of the pass transistor coupled to a word line, and a second source/drain region of the pass transistor coupled to a bit line. A plate line is coupled to the top plate of the capacitor to facilitate programming of the polarization state of a ferroelectric portion of the capacitor. The polarization state of the ferroelectric portion of the capacitor causes a depletion or accumulation of electrons in the bottom plate of the capacitor, thus altering its capacitance value. The resulting capacitance value may be sensed without causing a polarization reversal of the ferroelectric portion of the capacitor. Accordingly, bi-state ferroelectric memory cells of the various embodiments function as non-volatile memory cells.

Abstract: A communication system is described. The communication system includes a distribution network and a head end terminal adapted to transmit downstream control data and downstream telephony information in a first frequency bandwidth over the distribution network and adapted to receive upstream telephony information and upstream control data in a second frequency bandwidth over the distribution network. In addition the communication system includes a plurality of service units, each service unit operatively connected to the distribution network for upstream transmission of upstream telephony information and upstream control data in the second frequency bandwidth and for receipt of downstream control data and downstream telephony information in the first frequency bandwidth.

Abstract: Methods and apparatus for decoding an externally-applied address in a synchronous memory device are arranged to decode a first portion of the address during a setup time and to decode a second portion of the address following the setup time. The first portion of the address may be indicative of a bank address of a multiple-bank memory device. The second portion of the address may be indicative of row and column addresses within a bank of the multiple-bank memory device. Decoding of the first portion of the address is performed by an address input buffer stage having a decoder interposed between the input buffers and the address latches, such that the decoder generally replaces a delay stage of a typical input buffer stage. As such, the first portion of the address is decoded during a setup time. By decoding the first portion of the address during a setup time, it is available to direct the second portion of the address to a proper decoder substantially without delay.

Abstract: A circuit and method for synchronizing a service clock at a destination node with a service clock at a source node for circuit emulation service over a packet network. The method includes receiving data packets from a source node at at least one port of the destination node. At the destination node, the method removes from the data packets residual time stamp (RTS) values that were created at the source node based on at least the service clock at the source node. RTS values are stored in memory at the destination node. The method determines a majority count and a minority count of RTS values over a period of time from the RTS values stored in memory. The method further uses the majority and minority counts to set the frequency of a service clock at the destination node for use in receiving data packets.

Abstract: Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device wafer, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and a deposited oxide.

Abstract: A transmission system (10). The transmission system communicates data to a number of subscribers (14a, 14b). The transmission system includes a transceiver (12) that has a number of highly directional antennas (28). A number of digital repeaters (16a, 16b, 16c) are disposed in a geographic region serviced by the transceiver. The repeaters include a sectorized antenna that communicates with subscribers in a number of sectors of the geographic region of the repeater. The repeater also includes an upstream demodulator/modulator circuit (19). The upstream demodulator/modulator circuit demodulates data from signals from subscribers that were modulated with a first modulation technique, and generates a re-modulated signal with the data using a second modulation technique.