Abstract: A memory device can read data stored in memory cells using a differential voltage sensing technique. The memory includes a differential voltage sensing circuit having two input nodes. The nodes of the sensing circuit are pre-charged to an initial voltage level prior to reading the memory cell. The nodes can be pre-charged by charge sharing multiple bit lines. A reference current is coupled to a selected sensing node to increase the voltage potential of that node. At the same time, a word line signal is provided to a memory cell coupled to the selected node. If the memory cell is programmed, so that that it does not conduct current in response to the word line signal, the reference current increases the selected node such that the differential voltage sensing circuit can sense a differential between the two nodes. If the memory cell is not programmed, the memory cell conducts enough current to both discharge the selected sensing node and sink the reference current.

Abstract: A known clock frequency is divided into at least two phases, and the rising and the falling edges of each of the divided signals are counted. The sum total of edges in a given time period is compared to a stored sum of edges during an earlier time period of the same duration. Adjustment to the local clock is made if sufficient differences are detected.

Abstract: A system and method for conducting heat from electrical devices mounted on a circuit board is disclosed. A heat sink for conducting the heat is provided that includes a pair of substantially parallel vertical legs and a horizontal member coupled between the pair of substantially parallel vertical legs to form a “U” shape. The horizontal member includes an outer surface and an inner surface both having a layer of thermal interface material. The heat sink is surface mountable to a heat sink mounting pad on a surface of a printed circuit board. The heat sink mounting pad is adjacent to and thermally coupled to a heat transfer pad of an electronic device. The heat sink is thermally coupled to the electronic device.

Abstract: A transmission system (10). The transmission system communicates data to a number of subscribers (14a, 14b). The transmission system includes a transceiver (12) that has a number of highly directional antennas (28). A number of digital repeaters (16a, 16b, 16c) are disposed in a geographic region serviced by the transceiver. The repeaters include a sectorized antenna that communicates with subscribers in a number of sectors of the geographic region of the repeater. The repeater also includes an upstream demodulator/modulator circuit (19). The upstream demodulator/modulator circuit demodulates data from signals from subscribers that were modulated with a first modulation technique, and generates a re-modulated signal with the data using a second modulation technique.

Abstract: A collar is provided that has a sleeve having a tapered axial bore that defines a tapered surface interiorly of the sleeve. The tapered axial bore is adapted to receive a receptacle such that the tapered surface bears against the receptacle. Moreover, the collar has a resilient device that engages the sleeve. The resilient device, the tapered axial bore of the sleeve, and the receptacle receive a connector. Axial displacement of the connector relative to the sleeve and the receptacle compresses the resilient device such that the resilient device exerts an increasing axial force on the sleeve. The increasing axial force displaces the sleeve axially relative to the receptacle causing the tapered surface to exert a radial force on the receptacle.

Abstract: A video game system is described which includes a wireless game controller which stores information about the user of the controller. The controller includes a memory for storing the information. The information is communicated through wireless transmissions to a processor which can operate a video game. The personalized information can include, for example, the user's name, skill level, preferred characters, handicaps, limitations, and/or historical game scores. The game controllers can include a wireless receiver for receiving communications from the processor to update information stored in the controller. Several different communication operations and protocols are described, including storing a user identification code in the controller with corresponding detailed information stored in the processor, or storing detailed information in the hand held controller and down loading the information to the processor.

Abstract: A variable attenuator formed from a combination of PIN diodes is provided. The PIN diodes may be coupled in a “T,” “p” or other appropriate configuration. At radio frequencies (RF), a PIN diode acts as a variable resistor with a resistance value based on the bias current of the PIN diode. To control the attenuation level of the variable attenuator, the bias current of the PIN diodes are selectively adjusted. Digital values relating to selected bias currents, and thus selected attenuation levels, are stored in a memory. These digital values are provided as control signals that set the bias current levels for the PIN diodes. The bias current levels control the attenuation level of the variable attenuator.

Abstract: A method of staggering the arrival of frames of data at a head end in a communication system. The method includes receiving at a first service unit upstream telephony data is described. The telephony data includes a first payload message. The method includes receiving at a second service unit upstream telephony data, wherein the telephony data includes a second payload message. The method further includes formatting the first payload message at the first service unit as a first sequence of frames and formatting the second payload message at the second service unit as a second sequence of frames. In addition, the method includes transmitting the first sequence of frames on a first carrier so as to arrive at the head end at a first time and transmitting the second sequence of frames on a second carrier so as to arrive at the head end at a second time.

Abstract: A method for monitoring at least one telephony communication n-bit channel, wherein one of the bits is a parity bit, includes sampling the parity bit of the n-bit channel. A probable bit error rate is derived from the sampling of the parity bit. The probable bit error rate can be compared to a pre-determined bit error rate value to determine if the at least one telephony communication n-bit channel is corrupted. If the at least one telephony communication n-bit channel is corrupted, the at least one telephony communication n-bit channel is re-allocated to an uncorrupted and unallocated telephony communication n-bit channel. Further, at least one unallocated telephony communication channel can be periodically monitored and error data accumulated to indicate the quality thereof.

Abstract: A ring network for transporting data packets between network devices is provided. The ring network includes a number of ring switches. Each ring switch has at least one ring port, at least one local port and at least one table that self learns which network devices are associated with each port of the ring switch based on a selected source identifier from the packets processed by the ring switch. The source and destination identifiers may, for example, be a media access control (MAC) address from an Ethernet packet, an Internet Protocol (IP) address, at least a portion of a hierarchical address, a combination of two or more identifiers at different protocol levels for the data packet, a port number of a universal datagram protocol, or other appropriate identifier. The at least one ring port of each ring switch is coupled to a ring port of another ring switch in the ring network.

Abstract: A method of burst identification in a communication is described. The method includes receiving, at each of a first set of m service units, a plurality of modulated orthogonal carriers having information modulated thereon in a plurality of bands of a first frequency bandwidth transmitted from a head end terminal, wherein the first band includes at least one control channel. The method further includes scanning, at each of the m service units, the at least one control channel to detect identification information corresponding to each of the m service units to identify a particular band of the plurality of bands that each of the m service units is to use for receiving information from the head end terminal.

Abstract: A monitoring circuit is provided. The monitoring circuit can be used to monitor signals in a cable network. The monitoring circuit includes first and second stages. The first stage has an input and an output. The input is coupled to an external circuit. The first stage scales a voltage received at its input. The second stage is coupled to the output of the first stage. The second stage has a high input impedance and a low output impedance. The second stage buffers a signal at the output of the first stage to an output of the second stage.

Abstract: A memory device can read data stored in memory cells using a differential voltage sensing technique. The memory includes a differential voltage sensing circuit having two input nodes. The nodes of the sensing circuit are pre-charged prior to reading the memory cell. The nodes are pre-charged by charge sharing multiple bit lines. In one embodiment, local bit lines having a first charge are coupled to global bit lines having a second charge to provide a desired pre-charge level. The local and global bit lines can have equal capacitance values. The voltages of the bit lines prior to charge sharing can be any selected value, but in one embodiment the local bit lines are discharged to ground and the global bit lines are charged to Vcc.

Abstract: A compact disc handler includes a picker elevator containing a helically threaded lead screw journaled for rotation about a vertical axis and having a traveling nut thereon to which a disc picker arm is attached. A guideway in the tower cooperates with the picker arm to constrain the picker arm from rotating until reaching a predetermined height elevator. Using this design, a CD can be retrieved from an input hopper, placed in a label printer or other CD publishing/playing device and upon completion of same operation on the disc, it is transported by rotation to an output hopper.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the synchronous memory device comprises an array of memory cells arranged in rows and columns. A clock connection is provided to receive an externally provided clock signal. The memory does not require a precharge time period during a time period between the first and second externally provided active commands.

Abstract: A memory device can read data stored in memory cells using a differential voltage sensing technique. The memory includes a differential voltage sensing circuit having two input nodes. The nodes of the sensing circuit are pre-charged prior to reading the memory cell. The nodes are pre-charged by charge sharing multiple bit lines. In one embodiment, local bit lines having a first charge are coupled to global bit lines having a second charge to provide a desired pre-charge level. The local and global bit lines can have equal capacitance values. The voltages of the bit lines prior to charge sharing can be any selected value, but in one embodiment the local bit lines are discharged to ground and the global bit lines are charged to Vcc. The memory includes a programmable fuse circuit to selectively activate pass circuitry and couple one or more local bit lines to a global bit line in response to the pass command code. This allows the pre-charge level of the sensing nodes to be adjusted after fabrication.

Abstract: A memory device has multiple selectable read data paths. Some of the read data paths include compression circuitry to compress data and decrease test time by testing multiple memories in parallel and/or multiple array banks from the same memory in parallel. A non-compression read path is provided to by-pass the compression circuitry. During memory read operations, therefore, data can be coupled to output buffers without being subjected to delays through a compression circuit. A first compression path can be selected to couple 16 bits from 1 memory array bank to 4 output connections. A second compression path can be selected to couple 64 bits from 4 memory array banks to 4 output connections.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the present invention can include a memory device comprising an array of memory cells arranged in addressable blocks and an n-bit status register. The memory includes a control circuit coupled to the n-bit status register to program a first bit of the n-bits to a first state indicating if a program operation is being performed on the array. The control circuit further programs second and third bits of the n-bits to identify one of the addressable blocks while the array is being programmed. A method of operating a memory device includes initiating a write operation on a first programmable location of the memory device using a first processor, and reading a status from status data stored in the memory device during the write operation. The status indicates an identification of the first programmable location.

Abstract: Negative switch circuits are arranged to have a first electrical path coupled between an input and an output of the negative switch circuit and a second electrical path in parallel with the first electrical path for selectively isolating a load from a negative potential node. The first electrical path presents an open circuit in response to a first state of a first control signal and presents a closed circuit in response to a second state of the first control signal. The second electrical path presents an open circuit in response to either a first state of a second control signal or a condition of the load indicative of a defect associated with the load, and presents a closed circuit in response to a second state of the second control signal in combination with a condition of the load not indicative of such a defect. Such negative switch circuits are adaptable to isolate defective portions of a memory device from a negative charge pump during block erase operations.