Abstract: Memory devices having architectures permitting the application of a voltage differential across alternate bitlines facilitate identifying and locating shorts within the memory device with particular reference to flash memory devices. The memory devices include a first plurality of selective coupling devices coupled between a first plurality of bitlines and a first variable potential node. The memory devices further include a second plurality of selective coupling devices coupled between a second plurality of bitlines and a second variable potential node. The first plurality of selective coupling devices are responsive to a first control signal to selectively provide electrical communication between the first plurality of bitlines and the first variable potential node. The second plurality of selective coupling devices are responsive to a second control signal to selectively provide electrical communication between the second plurality of bitlines and the second variable potential node.

Abstract: A memory device provides a more efficient address decoding operation. In one embodiment, the memory device is a synchronous flash memory that has an array of memory cells arranged in rows and columns. An external device, such as a processor, provides row and column addresses for accessing the memory array. The memory device can include the internal address counter, such as a burst counter. The address processing circuitry includes address input buffers having a first latch circuit coupled thereto, and a multiplexer coupled to receive either the input address signals or addresses generated by the internal address counter. Second latch circuits are coupled to the multiplexer circuits. The second latch circuits, in one embodiment, latch the externally provided address signals coincident with the first latch circuit.

Abstract: A multi-point to point communication system. The system includes a distribution network between a head end terminal and a plurality of remote units, the head end terminal for downstream transmission of downstream control data and downstream telephony information in a first frequency bandwidth over the distribution network and for receipt of upstream telephony information and upstream control data in a second frequency bandwidth over the distribution network. The head end terminal including a head end multicarrier modem means for modulating at least downstream telephony information on a plurality of orthogonal carriers in a plurality of regions of the first frequency bandwidth and for demodulating at least upstream telephony information modulated on a plurality of orthogonal carriers of a plurality of regions in the second frequency bandwidth.

Abstract: An automatic gain control circuit for an analog to digital converter is provided. The automatic gain control circuit includes an input, coupled to an output of the analog to digital converter, to receive samples output by the analog to digital converter. The automatic gain control circuit also includes a digital to analog converter that is coupled to selectively adjust a magnitude of an input signal for the analog to digital converter. The automatic gain control circuit also includes a microcontroller. The microcontroller is coupled to the input and the digital to analog converter. The microcontroller is programmed to generate a feedback signal for the digital to analog converter to control the amplitude of the input to the analog to digital converter.

Abstract: A tension fastener includes a quick release feature. In one embodiment, the fastener has a moveable feature that can be used to maintain a compression force on a coil spring of the fastener. In one embodiment, the moveable feature is a pair of arms attached to the quick release head. The fastener can be used in a manufacturing environment having sifting tables to attach a sifting screen to a frame of the sifting table.

Abstract: The communication system includes a hybrid fiber/coax distribution network. A head end provides for downstream transmission of telephony and control data in a first frequency bandwidth over the hybrid fiber/coax distribution network and reception of upstream telephony and control data in a second frequency bandwidth over the hybrid fiber/coax distribution network. The head end includes a head end multicarrier modem for modulating at least downstream telephony information on a plurality of orthogonal carriers in the first frequency bandwidth and demodulating at least upstream telephony information modulated on a plurality of orthogonal carriers in the second frequency bandwidth. The head end further includes a controller operatively connected to the head end multicarrier modem for controlling transmission of the downstream telephony information and downstream control data and for controlling receipt of the upstream control data and upstream telephony information.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory includes a clock connection to receive an external clock signal, a chip select (CS#) connection to receive a chip select signal, a row address strobe (RAS#) connection to receive a row address strobe, a column address strobe (CAS#) connection to receive a column address strobe and a write enable (WE#) connection to receive a write enable signal. Control circuitry is provided to perform a burst read operation of memory cells in a first block of the memory and interrupt the burst read operation when the chip select signal is active, the row address strobe is either inactive or active, the column address strobe is de-active, the write enable signal is active, and the address signals identify the first block simultaneously during the burst read operation.

Abstract: An adjacent channel combiner combines an analog television channel with an upper adjacent digital television channel using practical filter designs. An aural signal of the analog television channel is combined after both a visual signal and a digital signal have been combined. A directional filter combines the visual and digital signals and a diplexer or other means is used for combining the aural signal with the combined visual and digital signal.

Abstract: The communication system includes a hybrid fiber/coax distribution network. A head end provides for downstream transmission of telephony and control data in a first frequency bandwidth over the hybrid fiber/coax distribution network and reception of upstream telephony and control data in a second frequency bandwidth over the hybrid fiber/coax distribution network. The head end includes a head end multicarrier modem for modulating at least downstream telephony information on a plurality of orthogonal carriers in the first frequency bandwidth and demodulating at least upstream telephony information modulated on a plurality of orthogonal carriers in the second frequency bandwidth. The head end further includes a controller operatively connected to the head end multicarrier modem for controlling transmission of the downstream telephony information and downstream control data and for controlling receipt of the upstream control data and upstream telephony information.

Abstract: Clock generator circuits containing a delay circuit having at least one delay element and at least one bypass are arranged to activate the bypass in response to a first logic level presented at the input of the delay circuit and to deactivate the bypass in response to a second logic level presented at the input of the delay circuit. Such clock generators are useful in synchronous memory devices for generating internal clock signals of fixed pulse width from an external clock signal. The internal clock signal is generated from a triggering event, such as a rising edge of the external clock signal, and has a pulse width determined by the delay time of the delay element. The first logic level is generated in response to the beginning of an output pulse of the clock generator while the second logic level is generated in response to the completion of an output pulse of the clock generator.

Abstract: A bidirectional multipoint-to-point communications system for sending payload information over a distribution network is provided. The system includes a head-end terminal coupled to the distribution network to a plurality of service units. The head-end terminal includes a head-end controller for sending payload data to and from an external communications network and for producing and processing control messages at the head-end terminal, a head-end multicarrier transmitting modem coupled to the head-end controller for modulating downstream payload information and downstream control messages onto multiple orthogonal carriers spread throughout substantially all of a first frequency band, and a head-end multicarrier receiving modem coupled to the head-end controller for demodulating multiple orthogonal carriers spread throughout substantially all of a second frequency band and carrying upstream payload information and control messages.

Abstract: A testing apparatus that comprises an electrical device. A first circuit is in electrical communication with the electrical device. The first circuit including an amplifier. First and second couplers are electrically connected to the first circuit and arranged in series with the amplifier. The amplifier is positioned between the first and second couplers. A second circuit has a first end in electrical communication with the first coupler and a second end in electrical communication with the second coupler. The total gain of the first coupler, the second coupler, the portion of the first circuit between the first and second couplers, and the second circuit is approximately zero.

Abstract: A motorcycle uses a unique suspension system to reduce front end dive during braking. Anti-dive characteristics through full suspension travel provides a smoother ride by reducing the compression damping used in the suspension. The suspension system incorporates a rigid fork, a compression fork and a rocker arm. The front wheel is mounted to the rocker arm such that an axis of the wheel is located along the rocker arm between the rigid fork and the compression fork. A brake is coupled to the axis of the front wheel with a first support member and is connected to the rigid fork with a second support member. A brake linkage which includes a portion of the rigid fork, the rocker arm, and the first and second support members forms an irregular quadrilateral during vertical movement of the front wheel, such that a centerline of the second support member and a centerline of the rocker arm intersect behind the front wheel axis.

Abstract: A system and method for conducting heat from electrical devices mounted on a circuit board is disclosed. A heat sink for conducting the heat is provided that includes a pair of substantially parallel vertical legs and a horizontal member coupled between the pair of substantially parallel vertical legs to form a “U” shape. The horizontal member includes an outer surface and an inner surface both having a layer of thermal interface material. The heat sink is surface mountable to a heat sink mounting pad on a surface of a printed circuit board. The heat sink mounting pad is adjacent to and thermally coupled to a heat transfer pad of an electronic device. The heat sink is thermally coupled to the electronic device.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can detect a brown-out of a supply voltage. The memory device comprises a voltage detection circuit to monitor a supply voltage and provide a signal if the supply voltage drops below a predetermined value. A latch is coupled to the voltage detection circuit and can be programmed to indicate if the supply voltage dropped below the predetermined value. An external controller can read a status of the latch. The memory, therefore, can provide an indication to an external controller that a reset, or initialization, operation is needed.

Abstract: A resonator filter comprising a housing formed with a conductive material. The housing defines a first cavity, a second cavity, and an intermediate wall positioned between the first and second cavities. The housing defines an opening between the first and second cavities. First and second center conductors are positioned within the first and second cavities, respectively. A coupling wire is connected between the first center conductor and the housing. The coupling wire and the center conductor have substantially equal thermal expansion coefficients.

Abstract: A network element for a virtual path ring network is provided. The network element includes a first ring interface module with a ring input and a ring output. Further, the network element includes a second ring interface module with a ring input and a ring output. A first bus is coupled to the first ring interface. A second bus is coupled to the second ring interface. The first and second ring interface modules each include a switch fabric that passes packets from the ring input of the interface module to its ring output for packets with a destination address for an endpoint associated with another network element. The switch fabrics of the first and second ring interfaces further pass packets from the ring input to the first and second buses, respectively, for packets with destination addresses for endpoints that are associated with the network element. An access interface module is coupled to the first and second buses that adds and drops traffic to and from the ring network.

Abstract: Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a “sub-bit” comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term “sub-bit” means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.

Abstract: A therapeutic hand exerciser includes a resilient core and a fabric exterior lining. The core is soft, pliable and smooth when squeezed. The soft smooth feel of a segmented polyurethane fabric, such as LYCRA®, also provides a more pleasurable feel than a rubber cover. The addition of the thermo plastic urethane (TPU) lining prevents the core material from passing through the fabric cover.