Abstract: A device for monitoring the anchor or anchor chain, intended for facilities floating ahead of the anchor, such as ships, comprising a measurement device which determines by one or more sensors the prevailing state at one or more points of an anchor chain or anchor, between the anchor chain and a ship, or between the anchor and the ship, then generates an electrical signal representative of the strength to a transmitter which, upon reception of the signal transmitted by the measurement device, sends a corresponding signal. An alarm system receives the signal sent by the transmitter and triggers an alarm if the measured state exceeds a set value.

Abstract: A system 100 fabricated on a single integrated circuit chip includes a microprocessor 101 operating from a high speed bus 102 and a peripheral bus 103 operating in conjunction with high speed bus 102 through a bus bridge 113. A first set of processing resources operate from high speed bus 102 and includes an external memory interface 108, a direct memory access engine 105 for controlling the exchange of information through memory interface 108, and a boot memory 104 for storing boot code. A second set of processing resources operate from peripheral bus 103 and includes an interrupt controller 115 for issuing interrupt requests to microprocessor 101, a set of programmable timers 117 for generating timed interrupt signals, and a phase locked loop 131 for generating timing signals.

Abstract: A data converter including a digital volume control for continuously scaling a received stream of digital audio data by a selected factor and a low noise delta-sigma modulator for re-quantizing a scaled digital data stream output from the digital volume control.

Abstract: A spread spectrum radio receiver configurable for use in both a quadrature phase shift keying (QPSK) and a frequency shift keying (FSK) environment. The receiver may include a programmably selectable zero crossing detector unit for use when the receiver is configured for the FSK environment and/or programmable low pass filters having variable cut-off frequencies. A common local oscillator may be used regardless of whether the receiver is configured for use in the QPSK or FSK environment.

Abstract: A method of amplitude control in a 1-bit digital system includes the step of scaling the stream of 1-bit data by a scaling factor corresponding to a selected output amplitude. The scaled data is modulated and the resulting modulated, scaled data is converted from digital to analog form.

Abstract: A method of extracting a clock from a biphase encoded bit stream includes the step of detecting a stream of samples each having a sample size measured between consecutive bit phase transitions. A sample length is determined for each sample, the sample length approximating a number of least common multiples in the corresponding sample size. A preamble is detected from the sample lengths of a sequence of the samples and decoded to determine an expected logic level of the clock following a transition at an expected clock edge. The expected level of the clock is gated with the biphase encoded data to generate a control signal in advance of the opening of the time window. The control signal is then gated with the biphase encoded data to extract the clock edge after the time window has opened.

Abstract: Clock generation circuitry 1300 includes an oscillator 1302 for generating a first signal from a crystal 1301 of a selected oscillating frequency. A first frequency multiplier 1304 selectively multiplies the frequency of the first signal by a predetermined factor to obtain a second signal having a frequency of a preselected multiple of a first set of clock signals. A divider 1305 selectively divides the frequency of the second signal by a second factor to obtain a third signal of a selected frequency.

Abstract: Circuitry for ramping a voltage across a load 506 includes a charging circuit 500 for charging a capacitor 501 to generate a ramp-up wave form. Circuitry 511 selectively decouples a first driver 510 from load 506 during a ramping up mode and couples first driver 510 to load 506 during a normal operating mode. Ramp up driver 507a is selectively coupled to the load 506 during the ramp-up mode for ramping up the voltage across load 506 in response to the ramp-up wave form generated by charging circuitry 500. A discharge circuit 503d, 514a,b discharges capacitor 501 to generate a power-down wave form. Circuitry 511 selectively decouples a first driver 501 from output load 506 during the ramping down of the voltage across output load 506. A ramp-down driver 507b selectively ramps-down the voltage across output load 506 in response to the ramp-down wave form generated by discharge circuitry 503d, 514a,b.

Abstract: A scheme for sharing a channel during a contention free period of communications between two or more basic service sets (BSSs) including network components in an overlapping region of a wireless computer network. These network components in the overlapping region may be configured to communicate in contention free periods only. Such bandwidth sharing may then include transmitting within each BSS exclusively during an allocated period of time. Each BSS may include one point coordinator network component and all other network components in the BSS then inform the point coordinator of channel conditions including degradation, and the number of packets received from other BSSs.

Abstract: A system 100 including a central processing unit 101 operates in response to a set of instructions for processing information. A port 134 provides access to selected circuitry forming a part of the system by an external device. A set of non-volatile programmable security elements 136 selectively enable and disable the operation of the interface to provide a private environment for processing the information.

Abstract: An integrated circuit includes a microcontroller core interconnected with a peripheral component interconnect (PCI) interface configurable as a PCI host/CPU bridge when the integrated circuit is used in embedded system applications and as a PCI device when the integrated circuit is used in a hosted application. In some cases, a radio media access controller is (MAC) interconnected to the microcontroller. Also, a forward error correction (FEC) coder/decoder (CODEC) coupled to the radio MAC may be provided. Such an FEC CODEC may be configured to provide Reed-Solomon coding/decoding. Preferably, one or more communication interfaces coupled to the microcontroller are provided, each being configured to allow for interconnection of the integrated circuit with external communication channels.

Abstract: A clock generator circuit includes a counter which counts edges of a received clock signal and a comparator which compares divide ratio control data with a count generated by the counter and generates an active state of a control signal in response. An output flip-flop toggles in response to the control signal and a selected edge of the received dock signal to toggle a state of an output clock signal.

Abstract: An apparatus and method for memory transaction buffering are implemented. Read and write buffer units are provided. The read buffer unit is configured for storing at least one data value read from a memory device, and the write buffer unit is configured for storing at least one data value for writing to the memory device. The read buffer unit is operable for updating with the at least one data value for writing to the memory device in response to a write to the write buffer unit.

Abstract: A noise shaper including first and second quantizers and first and second feedback paths each providing feedback from a corresponding quantizer output. A loop filter system implements a plurality of transfer functions including a first non-zero transfer function between the first feedback path and an input of the first quantizer, a second non-zero transfer function between the first feedback path and an input of the second quantizer, a third non-zero transfer function between the second feedback path and the input of the first quantizer and a fourth non-zero transfer between the second feedback path and the input the second quantizer.

Abstract: A delta-sigma modulator for driving an output stage is disclosed. The delta-sigma modulator operates between first and second voltages and includes a loop filter, a quantizer, and a feedback loop coupling an output of the quantizer and an input of the loop filter. The feedback loop includes compensation circuitry for compensating for variations in the first and second voltages in response to a measured average of the first and second voltages and a measured difference between the first and second voltages. Measuring circuitry measures the average and the difference of the first and second voltages.

Abstract: A method and system for improving networking performance in networks based on lossy channels. A selected file system call 109 is redirected by sending a file request to a server over a first protocol. Data is received from the server in response to the file request over a second protocol.

Abstract: A noise shaper including a filter system for generating a first set of poles and zeros characterizing noise attenuation in a signal baseband of a noise transfer function and at least one additional set of at least one pole and one zero characterizing noise attenuation in at least one additional band outside the baseband of the noise transfer function.

Abstract: A variable color optical device repeatedly develops a start signal and two end signals respectively timed in relation to the start signal in accordance with the values of two sets of data. Two stable signals are developed, each from the start signal to the respective end of signal. Two control signals are applied, in accordance with the two stable signals, for respectively forwardly biasing the light emitting diodes of two primary colors.

Abstract: A digital to analog converter including a noise shaping modulator for modulating an input digital data stream, a plurality of output elements for generating a plurality of intermediate data streams from a modulated output stream from the modulator, and an output summer for summing the intermediate data streams to generate an output analog stream. The noise shaping modulator balances an edge transition rate of the output elements, such that the edge transition rate of two selected elements is approximately equal.

Abstract: A noise shaper includes a first feedback loop for noise shaping a first feedback signal under normal operating conditions and having a first filter with a first signal transfer function and a second feedback loop that is stable under overload conditions and has a second filter having a second signal transfer function differing from the first signal transfer function. The noise shaper also includes an output circuit block including a quantizer and steering circuitry. The quantizer includes an input simultaneously responsive to outputs of the first and second filters. The steering circuitry steers a feedback from an output of the quantizer to input of the first and second feedback loops. The steering circuitry steers feedback from output of the quantizer to inputs of the first and second feedback loops, the steering circuitry including a first output for providing the first feedback signal to the first feedback loop and a second output for providing a second feedback signal to the second feedback loop.