Abstract: A system and method for compensating switched mode amplifiers. The amplifier system includes an adaptive filter coupled to the output of circuitry that recovers the analog signal from the output of the switching amplifier circuitry. The adaptive filter derives an inverse transfer function of the forward path through the system. The derived inverse transfer function is used to generate a coefficient map which a compensation filter responsively compensates for from variations in the output load of the amplifier system. In the disclosed method, the deriving the inverse transfer function may further include calibrating the adaptive filter continuously, at system startup or in response to user demand.

Abstract: A method and a circuit of performing an analog to digital conversion in a charge redistribution circuit including a capacitor array of weighted capacitors and a transistor track switch for sampling an input signal into the capacitor array. A common mode voltage is stepped to a voltage sufficient to turn on the transistor track switch during a sampling phase. During the sampling phase, a top plate of each of the capacitors is coupled to the common mode voltage through the track switch while the bottom plate of each of the capacitors is coupled to an input to sample an input signal. During a conversion phase, the top plate of each of the capacitors is decoupled from the common mode voltage and the bottom plates of a selected one of the weighted capacitors is coupled to a first reference voltage, a weight of the selected one of the weighted capacitors proportional to the step in the common mode voltage.

Abstract: A method of operating a cache memory includes the step of storing a set of data in a first space in a cache memory, a set of data associated with a set of tags. A subset of the set of data is stored in a second space in the cache memory, the subset of the set of data associated with a tag of a subset of the set of tags. The tag portion of an address is compared with the subset of data in the second space in the cache memory in that said subset of data is read when the tag portion of the address and the tag associated with the subset of data match. The tag portion of the address is compared with the set of tags associated with the set of data in the first space in cache memory and the set of data in the first space is read when the tag portion of the address matches one of the sets of tags associated with the set of data in the first space and the tag portion of the address and the tag associated with the subset of data in the second space do not match.

Abstract: A single variable color display device simultaneously exhibits two distinct display units in a side by side relation. Two color controls are provided for illuminating the display units in respectively different colors so they could be readily distinguished.

Abstract: A computer system includes a register file and an arithmetic logic unit (ALU) for reading data from the register file. The ALU is configured to conduct data processing of the data which was and to store the results of the data processing in the register file. The computer system further includes a condition code stack configured to hold data indicative of the context results of the data processing by the ALU. The ALU is further configured to query the condition code stack for predetermined bit values to determine operations controlled by the ALU. In particular, value of a specified data item in a condition code stack is queried, and the queried value of the data item is used to implement transfer control.

Abstract: Data is transmitted over a computer network from a source network component to one or more destination network components. Thereafter, one or more acknowledgements are transmitted from one of the destination network components to the source network component; and different data, which may include retransmissions, from the previously transmitted data is transmitted from the source network component to the one or more destination network components. A negative acknowledgement message from the destination network component may be transmitted to the source network component upon a failure to receive one or more of the transmitted data packets, the negative acknowledgment including packet identifications of said one or more data packets. Then data packets identified by the identifications received in a negative acknowledgement may be retransmitted before transmitting other packets. The negative acknowledgements thus indicate failed receipt of data. Positive acknowledgements indicate successful receipt of data.

Abstract: A switched- capacitor summer 400 includes an operational amplifier 206 having an input and an output, first and second parallel capacitors 307, 401, first switching circuitry 308, 404 and second switching circuitry 402, 403. First switching circuitry 308, 404 discharges first capacitor 307 during a first timing phase and couples second capacitor 401 between the input and the output of operational amplifier 306 during a first timing phase. Second switching circuitry 402, 403 couples a first capacitor 307 between the input and output of operational amplifier 306 during the second phase to transfer charge from capacitor CS to capacitor 307 and charge up capacitor CH during the second phase.

Abstract: A return path for use in a switched capacitor circuit includes an array of capacitors and a plurality of switches for selectively coupling voltages to capacitors. A set of latches selectively controls the plurality of switches during time periods partitioned into non-overlapping reset and set cycles. During a first such time period, a selected one of the capacitors is decoupled from a current voltage during the reset cycle and coupled to a selected reference voltage during the set cycle.

Abstract: Disclosed is a data converter and a method for converting a digital audio stream representing an analog signal that has been sampled at a certain rate. The circuit includes a divider that receives a clock signal associated with the digital audio stream and divides the clock signal by a selectable division factor. The division factor is set according to divider control signals. At the output of the divider is provided an internal clock signal. A frequency detection circuit receives the signal from the output of the divider, and the frequency detection circuit detects the original sampling rate of the audio signal based upon intrinsic characteristics (e.g., MCLK to LRCK ratio) of the digital audio stream.

Abstract: A delta-sigma modulator 400 includes circuitry 407 for selectively varying an order of the modulator to vary a modulation index of the delta sigma modulator.

Abstract: Servo control circuitry 300 includes a digital to analog converter 402 for converting digital servo control data into a pulse width modulated signal. A first conductor transmits the pulse width modulated signal to an external device 409. A second conductor transmits a reference signal derived from the clock signal to external device 409, external device 409 differentially receiving the pulse width modulated signal with respect to the reference signal.

Abstract: Processing digital information made up of a plurality of n-bit samples is performed by raising each n-bit value to an x-bit value, x being greater than n. The x-bit values represent mid-band values, wherein in this context a band includes a sequential set of x-bit values having n most significant bits in common and a mid-band value is then an x-bit value approximately centered between the lowest and highest x-bit values of a band including that mid-band value. In some embodiments, the digital information may comprise video information. Thus, the process may be applied prior to converting the video information from a first color space (e.g., a red-green-blue (R-G-B) color space) to a second color space (e.g., a luminance-chrominance (Y-Cr-Cb) color space). For a particular embodiment, n may be equal to five or six, and x may be equal to eight, however, in general n may be variable amongst different ones of the samples.

Abstract: A driver circuit 605 including a p-channel transistor 606 for driving an output from a supply rail at a positive supply voltage, p-channel transistor 606 disposed in an n-well. A detector 500 detects ramp down of the supply voltage below a preselected threshold voltage while a power reservoir 301 maintains a preselected well voltage of the n-well after the supply voltage ramps down below the preselected threshold.

Abstract: A sample rate converter for converting a data stream having a first base sampling frequency to a data stream having a second base sampling frequency. Up-sampling circuitry receives first oversampled data having a first oversampling ratio with respects to the first base frequency and outputs second oversampled data having a second oversampling ratio with respects to the first base sampling frequency. Resampling circuitry resamples the second oversampled data by a resampling frequency ratio of integers representing a ratio of the first and second base frequencies and generates third oversampled data having the second oversampling ratio with respects to the second base frequency. Down-sampling circuitry then down-samples the third oversampled data and generates fourth oversampled data having the first oversampling ratio with respects to the second base frequency.

Abstract: A method of compensating for finite common mode rejection in a switched capacitor circuit including arrays of input capacitors coupled to first and second differential nodes, includes the step of sampling a common mode voltage onto the differential nodes during a sampling phase. The input capacitors are then coupled to a ground node against which the common mode voltage is referenced to capture an offset voltage between the first and second differential nodes. The voltage offset is then subtracted out.

Abstract: A multicolor display element includes a plurality of display areas arranged in a pattern. Each display area includes three light emitting diodes for emitting light signals of respectively different colors. The light emitting diodes of the same color are commonly coupled to three buses, respectively, which may be activated in selective combinations by a gate network, to illuminate the display areas in a selective blended color.

Abstract: A level shifter 200 for shifting a logic high voltage of an input signal from a lower voltage to a higher voltage includes a latch 204 for storing a bit of data and having an output for driving a stored logic high bit at the higher voltage. A data node is coupled to a source of the higher voltage and an input of the latch. Voltage control circuitry 203 selectively gates the input signal received at the lower voltage with a bit of data stored in latch 204 and selectively pulls down the voltage at the data node in response.

Abstract: An output stage 300 includes a first output switch 201 having a current path for driving an output from a first voltage rail and a second output switch 202 having a current path for selectively driving the output from a second voltage rail. A first reference switch 301 is scaled with respects to first output switch 201 and has a current path coupled to the first voltage rail. A second reference switch 302 scaled with respects to second output switch 202 has a current path coupled to a current path of first reference switch 301 at a node and the second voltage rail. The logic measures an impedance mismatch between first and second reference switches 301, 302 and proportionally varies the impedance of a selected one of first and second output switches 201, 202 in response.

Abstract: An instrumentation circuit has an integrated circuit that has input terminals, an amplifier arrangement using feed forward compensation and an analog to digital converter and a serial data output receiving the output from said amplifier arrangement. A bridge circuit, having a transducer, or a thermocouple arrangement are connected to input terminals of the integrated circuit.

Abstract: An apparatus and method for power digital-to-analog converter protection are implemented. An attenuation value is set in response to the value of the supply voltage. The attenuation value is provided to a gain control, along with the input signal. A gain, offset by the attenuation value, determines the gain-adjusted output signal of the gain control generated from the input signal.