Abstract: An amplifier is disclosed including multiple integrator stages. The amplifier includes a low-frequency path from a signal input to a signal output and relatively higher-frequency bypass paths around the first integrator stage. The paths converge at a summing node. To prevent instability when the integrators are saturated by large signals, the circuit includes a saturation detector which disables the relatively low-frequency paths during such saturation conditions.

Abstract: A data processing system 100 is provided which includes a memory 104, an array 204 of memory cells arranged in rows and columns, each row being addressable by an address. Address generation circuitry 201/202 is provided for generating ones of the addresses for accessing selected ones of the rows in the array 204. An associative memory 203 is coupled to the address generation circuitry 201/202 for translating a first address, received from the address generation circuitry 201/202 and addressing a defective one of the rows of the array 204, into a second address addressing an operative one of the rows in array 204, the second address being sent to the memory.

Abstract: A memory system 20 includes a first array 100 and a second array 102 of memory cells. The memory system allows for a quick transfer of the contents of one of the arrays with another one of the arrays. Through the use of a transfer gate (128) interposed between column decoders (150 and 152) corresponding to the two memory arrays, data may be transferred between the two arrays in a single timing cycle. Furthermore, even given the interconnection between the two memory arrays due to the transfer gate, the two memory arrays can be operated independently of one another, with respect to address, data, and timing information.

Abstract: A switched capacitor circuit (300) including an operational amplifier (206) having an input and an output, a sampling capacitor (203) and a set of switches (204, 205, 301, and 302) are disclosed. During a first phase, switches (201, 204) sample an input voltage by charging sampling capacitor (203). During a first portion of a second phase, the operational amplifier input is electrically coupled to sampling capacitor (203) through a first path including switch (301) having a first time constant. During a second portion of the second phase, the operational amplifier input is electrically coupled with sampling capacitor (203) through a second path including switch (302) having a second time constant, the second time constant being smaller than the first time constant.

Abstract: A multiprocessor processing 200 includes a memory system having a memory controller 202 for linking a plurality of processors 201 with an integrated memory 203. Integrated memory 203 comprises a plurality of static random access arrays 603 and a dynamic random access 407.

Abstract: An asymmetrical switching element including a random access memory element, a first port selectively coupled to the memory element by first control signal and a plurality of second ports, each independently coupled to the memory element by corresponding one of a plurality of second control signals.

Abstract: A shift register includes a plurality of shift register stages having inputs and outputs coupled to form a chain. Each stage includes enable and disable control inputs, with an output of a selected one of the stages coupled to the enable input of a stage a selected number of stages ahead in the chain and to the disable input of a stage a selected number of stages behind in the chain.

Abstract: A sample rate converter 210, 209 includes a filter 210 for processing digital data in response to a clock controlled by a clock enable signal, the filter 210 receiving the digital data at a first sampling rate and outputting digital data at a second sampling rate. Resampler circuitry 209 generates first selected periods of the clock enable signal having a first duty cycle approximating a ratio between the first sampling rate and the second sampling rate. Selectively, selected periods of the clock enable signal are generated having a second duty cycle for minimizing an error accumulated over the first selected periods of the clock enable signal.

Abstract: Bandwidth within a common wireless communication channel used by a number of independent computer networks is allocated by assigning a portion of the total bandwidth of the common wireless communication channel to intra-network communications in each of the independent computer networks. This bandwidth allocation scheme may, from time to time, involve revising existing bandwidth allocations for one or more of the independent computer networks, for example when new networks or new clients in existing networks request bandwidth within the channel. The intra-network communications may occur within a slotted link structure that includes transmission times for master and client devices of the respective network. These transmission times are preferably arranged within a hierarchy that includes transmission times for master and client devices of other networks that share the wireless communication channel.

Abstract: A buffer arrangement uses separate amplifiers for handling for positive going signal transitions and for negative going signal transitions respectively. A comparator detects the direction of transition and a switching element connects signal input lines in the appropriate sense to the respective amplifiers based on the output of the comparator. This permits amplifiers optimized for positive or negative going transitions to be used.

Abstract: A method of gain scaling in a charge redistribution analog to digital converter includes the step of segmenting a bit weighted capacitor array into a first segment having at least one capacitor representing a least significant bit and a second segment having at least one capacitor representing a most significant bit. During a sampling phase, an input signal is sampled onto the at least one capacitor of the second segment while the at least one capacitor of the first segment is coupled to a fixed voltage.

Abstract: A device for monitoring the anchor or anchor chain, intended for facilities floating ahead of the anchor, such as ships, comprising a measurement device which determines by one or more sensors the prevailing state at one or more points of an anchor chain or anchor, between the anchor chain and a ship, or between the anchor and the ship, then generates an electrical signal representative of the strength to a transmitter which, upon reception of the signal transmitted by the measurement device, sends a corresponding signal. An alarm system receives the signal sent by the transmitter and triggers an alarm if the measured state exceeds a set value.

Abstract: Disclosed in this application is the placement of an additional integrator between the first stage integrator output and the input to the attenuator/low pass filter. This approach reduces the input referred offset by a factor equal to the gain of the additional integrator, and the offset of the additional integrator itself will be divided by the gain of the first-stage integrator.

Abstract: An interface 400 for interfacing an optical pickup 101 is associated with processing circuitry 100. A plurality of inputs receive data retrieved from an optical disk by the pickup and 401, 402, 403 are each coupled to a corresponding one of the inputs and independently activated and deactivated to selectively pass the data to the processing circuitry.

Abstract: A portable radio telephone handset includes the capability of operating as a data transfer terminal as well as an analog cellular telephone subscriber station. Two modes of operation are available in the handset, an analog cellular communication mode and a Cellular Digital Packet Data (CDPD) mode. A paging function for incoming analog cellular communication is carried out on a CDPD channel. The handset distinguishes between paging signals identifying CDPD mode communications and paging signals identifying analog cellular communications. The handset automatically preempts CDPD communications in favor of analog cellular communications such as those carried out in an AMPS configuration. To maintain the security of the handset ID, AMPS communications can be set up and controlled using CDPD control channels.

Abstract: A switched capacitor circuit includes a plurality of capacitor arrays coupled to a node, including an input array, a trim array associated with a selected capacitor of the input array and an offset compensation array. A first plurality of switches selectively couple capacitors of the input and trim arrays to selected reference voltages to approximate an impedance presented at the node during a subsequent operation to trim the selected capacitor of the input array. A sampling switch samples the selected reference voltages onto the input and trim arrays, the sampling switch injecting a corresponding amount of charge on the node. A second plurality of switches then selectively couples capacitors of the offset compensation array to the selected reference voltages to compensate for the amount of charge injected onto the node.

Abstract: An interface for coupling a modem port with a transmission line includes a hybrid converter having a variable gain amplifier coupling a transmit path of a first differential polarity and a received path of a second differential polarity.

Abstract: A low power, low area shift register permits control over delay by dividing the shift register cells into a plurality of segments that are serially connected. A first selector provides data from a shift register input selectively to an input of one of the segments. A second selector provides data from an input or output of a selected cell of one segment of shift register cells to a shift register output.

Abstract: A portable radio telephone handset includes the capability of operating as a data transfer terminal as well as an analog cellular telephone subscriber station. Two modes of operation are available in the handset, an analog cellular communication mode and a Cellular Digital Packet Data (CDPD) mode. A paging function for incoming analog cellular communication is carried out on a CDPD channel. The handset distinguishes between paging signals identifying CDPD mode communications and paging signals identifying analog cellular communications. The handset automatically preempts CDPD communications in favor of analog cellular communications such as those carried out in an AMPS configuration.