Patents Represented by Attorney, Agent or Law Firm James R. Burdett
  • Patent number: 6515482
    Abstract: An ionization vacuum gauge which can stably perform measurements of pressure in the intermediate vacuum to high vacuum regions, that is performed by an ionization-type first measurement element, as well as in the measurement region intrinsic to a second measurement element. This ionization vacuum gauge comprises a measurement element vessel, and first and second measurement parts provided within this measurement element vessel. The first measurement part comprises component electrodes including a filament, grid and ion collector, and is of an ionization-type construction for measurement of the pressure of vacuum states. The second measurement part is of a construction having different functions from those of the first measurement part, and is disposed in a space that is near the extension of the grid axis, and is away from the principal space for flying of thermal electrons emitted from the filament.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: February 4, 2003
    Assignee: Anelva Corporation
    Inventor: Yousuke Kawasaki
  • Patent number: 6511794
    Abstract: A method of forming a resist pattern and an exposure device using the method are provided in which a relatively large pattern, whose dimension is greater than a resolution limit of a KrF exposure technique, and an extremely fine pattern, whose dimension is less than or equal to the resolution limit of the KrF exposure technique, can be formed well and simultaneously. Two patterns are exposed simultaneously by deep UV light of a wavelength of 248 nm on a resist film 10 formed of TDUR-P015 and formed on a surface of an SiO2 film 12. The two patterns are: a circular pattern of a dimension which is made larger, in accordance with a shrinkage rate, than a finally required pattern dimension, which circular pattern is formed at regions to be shrunk; and a circular pattern of a dimension which is finally required, which circular pattern is formed at regions not to be shrunk.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: January 28, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takamitsu Furukawa
  • Patent number: 6496042
    Abstract: A phase comparator which eliminates jitter in a clock signal extracted in a phase locked loop. The phase comparator includes: a flip-flop circuit which inputs input data and the clock signal and stores the input data in response to the clock signal; a delay circuit which inputs the input data and delays the input data by a predetermined angle of 0° through 180°; a first logic gate which inputs the input data and an output signal of the flip-flop circuit and which outputs an output signal by taking an exclusive OR or exclusive NOR thereof; and a second logic gate which inputs the data and the output signal of the delay circuit and which outputs an output signal by taking an exclusive OR or exclusive NOR thereof.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: December 17, 2002
    Assignee: Oki Electric Industry, Co., Ltd.
    Inventor: Satoshi Nishikawa
  • Patent number: 6487215
    Abstract: An ATM signal generator generates packet signals by linking N data blocks that includes user data and a specifier byte containing a sequence number bit. A transmitter receives the packet signals, generates control signals containing length information, generates N−1 ATM cells accommodating one data block in the payload, generates one ATM cell accommodating one data block and a control signal in the payload, and transmits all of the ATM cells to a communications path. A receiver receives ATM cells from the communications path, detects the number of cell rejections using the sequence number bits extracted from the specifier bytes in all of the ATM cells, and detects the number of bit error occurrences using the length information extracted from the control signals.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: November 26, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kazuhiro Watanabe, Satoshi Owada
  • Patent number: 6481717
    Abstract: A method of playing a card game is made up of steps dealing a first hand consisting of a first predetermined number of cards, requiring one or more players to each elect whether or not to play a second hand, comparing each of the first hands to determine whether or not they constitute a winning hand, dealing a second hand consisting of a second predetermined number of cards and including the first hand, comparing each of the second hands using a predetermined ranking as a criterion for comparison to determine a winning hand, and designating as a winner each player who had a winning first hand and/or a winning second hand. The first predetermined number of cards consists of two cards, and the first hand is played as a Blackjack hand. The second predetermined number of cards consists of a number of cards, in addition to the cards drawn by each player for the Blackjack hand, to make up a poker hand.
    Type: Grant
    Filed: January 24, 2000
    Date of Patent: November 19, 2002
    Assignee: Iroc Worldwide Gaming, Inc.
    Inventor: James J. Richardelle
  • Patent number: 6480081
    Abstract: A shock sensor includes a casing defining a cylindrical space therein. The sensor also includes a protecting tube placed the cylindrical space so as to define an annular space between the casing and the protecting tube, the protecting tube having an inner space therein. A partitioning member is provided in the inner space so as to extend parallel to the longitudinal axis of the protecting tube and to divide the inner space into a plurality of compartments extending substantially parallel to the protecting tube. The sensor also includes a plurality of reed switches positioned one in each of the compartments, and insulating members placed in remaining spaces in the compartments. A magnetic actuating device for actuating the reed switches when a shock of predetermined magnitude acts on the sensor is slidably disposed on the protecting tube.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: November 12, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kiyotaka Nakamura
  • Patent number: 6469824
    Abstract: A low cost L-band EDF (erbium doped fiber) amplifier offering high safety for human beings. Signal light and forward pumping light enter from the front end of the EDF. Amplified signal light exits and backward pumping light enters from the rear end of the EDF. The signal light that exits the rear end of the EDF isoutput from an optical connector. The power of the output signal light is set to its normal value when an optical fiber is connected to the optical connector, but is reduced to a level safe for the human body when an optical fiber is not connected to the optical connector. When the output signal light power is reduced, the forward pumping light power is reduced to a prescribed value that is not zero, and the backward pumping light power is reduced to zero. Where the backward pumping light power is zero, the output signal light power depends solely on the forward pumping light power. Therefore, the output signal light power can be reduced to a safe level using a simple control circuit.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: October 22, 2002
    Assignee: Oki Electric Industry, Co., Ltd.
    Inventor: Akira Sasaki
  • Patent number: 6459110
    Abstract: A memory cell array, in which a voltage that can reverse polarization is applied only to a memory cell that is an object of data writing. A semiconductor storage element is formed by a ferroelectric capacitor, a selection transistor and a control transistor. The ferroelectric capacitor is structured to be provided with a ferroelectric layer between an upper electrode and a lower electrode. The selection transistor is provided with a first main electrode, a second main electrode and a control electrode. The control transistor is provided with a first main electrode, a second main electrode and a control electrode. The lower electrode of the ferroelectric capacitor is connected with the first main electrode of the selection transistor. The second main electrode of the selection transistor is connected with the control electrode of the control transistor.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: October 1, 2002
    Assignee: Oki Electric Industry, Co., Ltd.
    Inventor: Kouichi Tani
  • Patent number: 6427403
    Abstract: An entire structure utilizing fiber reinforced plastic (FRP) pultruded structural shapes is provided for use in decks, docks, and boardwalks. This deck system for building decking, docks, boardwalks, walkways, gazebos, hot tub decks and spas can be built either to and extending from the exterior side of residential or commercial structures or as an independent, freestanding structure. The invention is assembled from FRP pultruded components comprising several systems which include a weight bearing support system, flooring system, safety system, roofing system, and decorative system. Components of the invention including but not limited to vertical support posts, horizontal decking, railing, stairs, gates, doors, frames and supporting members will be manufactured from FRP pultrusion structural shapes and composite sections using corrosion resistant hardware and adhesives.
    Type: Grant
    Filed: November 3, 1998
    Date of Patent: August 6, 2002
    Inventor: Nicholas C. Tambakis
  • Patent number: 6420734
    Abstract: An LED is provided with a p-type semiconductor region in the shape of an island being buried in an n-type semiconductor region from the surface of it, and forms a pn junction at the interface between these n-type region and p-type region. The pn junction has a bottom junction at the bottom of the n-type region and a side junction at the peripheral side face. The bottom junction comprises a first subjunction being deep and constant in junction depth and a second subjunction varying continuously in junction depth. The depth of the second subjunction is shallower than the depth of the first subjunction. The p-type region portion above the second subjunction is thinner in thickness than the p-type region portion above the first subjunction. A light passing through the p-type region portion of the former is less in absorptior and more in optical power of the output light. The total power of the output light of the whole LED is increased correspondingly to reduction in thickness of the p-type region.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: July 16, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makoto Ishimaru
  • Patent number: 6418400
    Abstract: An improved “code-free” method of describing EDI business information manipulation processes. Whereas currently EDI translation and message processing is characterized by complex programming methods, this use of a spreadsheet style metaphor enables EDI processing to be developed that can be used in an ad hoc and dynamic fashion. This matches the business requirements brought about by environments such as the Internet and Electronic Commerce. Also the method can be integrated directly into modern software tools such as Web Browser software, and used by people who are not intimately familiar with the exact details of EDI message syntax. Instead they utilize a familiar data representation in order to accomplish a complex task that otherwise would instead require highly skilled programming knowledge to perform.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: July 9, 2002
    Assignee: XML-Global Technologies, Inc.
    Inventor: David R. R. Webber
  • Patent number: 6407410
    Abstract: A light emitting diode in accordance with the present invention has a p-n junction which is formed by selectively implanting an impurity from the surface of a semiconductor substrate, and also has an etched groove which is formed in the p-n junction area near the surface of the substrate. In the area where the etched groove is formed, the p-type area and the n-type area are spatially separated in the region of the substrate, therefore the movement of minority carriers does not occur. As a consequence, in the light emitting diode in accordance with the present invention, the movement of minority carriers in the p-n junction interface occurs at a deeper position of the semiconductor substrate. In a deep position of the semiconductor substrate, the recombination rate of minority carriers is high. Therefore if the recombination of minority carriers is increased in a deep position, the emission efficiency of the light emitting diode increases.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: June 18, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Mitsuhiko Ogihara, Yukio Nakamura, Hiroshi Hamano, Masumi Taninaka
  • Patent number: 6396117
    Abstract: Light on the longer wavelength side can be photoelectrically converted and output reliably, whilst improving the structural and operational reliability of a photodetector, by means of a simple manufacturing process and inexpensive manufacturing costs. A first light-absorbing layer, a buffer layer of a second conductivity type, a second light-absorbing layer of a second conductivity type and a window layer of a second conductivity type are laminated in this order onto the first principal surface of a substrate of a first conductivity type. The first light-absorbing layer contains a region of the first conductivity type and a region of the second conductivity type, and a diffused region of the first conductivity type having a depth extending from the upper face of the window layer to the interface between the window layer and the second light-absorbing layer is provided in a portion of the window layer.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: May 28, 2002
    Assignee: Oki Electric Industry Co., LTD
    Inventors: Ryozo Furukawa, Masanobu Kato
  • Patent number: 6386511
    Abstract: To be able to reduce the size of a drive part and, as a result, to achieve the reduction in size and the lowering of manufacturing cots of a gate valve. An open/close mechanism is configured from a turning pair only. This open/close mechanism is configured from a first swing link, second swing link and coupling link. The first swing link is driven by a rotation cylinder to perform a swinging motion. The second swing link is connected to a drive shaft and performs a swinging motion with the drive shaft as its axis. The first swing link and second swing link are coupled by the coupling link. When the rotation cylinder is driven, whereby the first swing link is caused to swing, the coupling link is vertically driven whereby the second swing link is caused to swing. As a result, a valve, connected to the second swing link, swings and the opening and closing operation of the flow path port is performed.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: May 14, 2002
    Assignee: Anelva Corporation
    Inventors: Kazuhito Watanabe, Yoshihiro Katsumata, Nobuyuki Takahashi
  • Patent number: 6374018
    Abstract: An optical switch in which operational ranges of both a bar state and a cross state are wide is provided. By applying voltages of +V, −V, −V and+V independently to a first electrode 20A, a second electrode 20B, a third electrode 20C and a fourth electrode 20D, switching control to the bar state or the cross state is carried out.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: April 16, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hideaki Okayama
  • Patent number: 6356157
    Abstract: The Phase Locked Loop circuit of this invention has both a short locking time and a stable operation. This Phase Locked Loop circuit has two phase comparators. The inputs to these two comparators are a reference signal Vf and a feedback signal Vc. The first phase comparator has two separate outputs depending on the phase difference &dgr; between the signals Vf and Vc. The first output is a signal up1 when &dgr; is smaller than −&tgr;1, and the second output is a signal dn1 when &dgr; is larger than −&tgr;1. The second phase comparator also has two outputs depending on the phase difference &dgr; between the signals Vf and Vc. The first output is a signal up2 when &dgr; is smaller than −&tgr;2 (&tgr;2>&tgr;1), and the second output is a signal dn2 when &dgr; is larger than &tgr;2. The signals up1 and up2 are output when the &dgr; has positive polarity and large absolute value. When &dgr; has positive polarity and a small absolute value, only signal up1 is output.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: March 12, 2002
    Assignee: Oki Electric Industry, Co., Ltd.
    Inventor: Yukio Kawamura
  • Patent number: 6351194
    Abstract: An electronic component having a multi-layered printed circuit board made of an organic material, a plurality of electronic components mounted in a face-down position on the multi-layered printed circuit board, a metal cover for covering the plurality of electronic components remaining a space or a cavity between the top surface of the printed circuit board and the inner surface of the metal cover having a flange surrounding the outskirts of the metal cover to be adhered to the top surface of the multi-layered printed circuit board, and a heat conductive member packed between the bottom surface of the electronic components, wherein the multi-layered printed circuit board has at least one through-hole vertically penetrating the multi-layered printed circuit board at a location corresponding to the flange and is lined by a metal film, and the multi-layered printed circuit board has a heat conductive layer arranged along the rear surface of the multi-layered printed circuit board, the heat conductive layer being
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: February 26, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yoshiro Takahashi, Kei Nakakuki, Satoshi Itaya, Kayo Hamano
  • Patent number: D458841
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: June 18, 2002
    Assignee: Saga Software, Inc.
    Inventors: George J. Goguen, Jonathan Daniel McVey
  • Patent number: D459986
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: July 9, 2002
    Assignee: Graham Packaging Company, L.P.
    Inventor: Sheldon E. Yourist
  • Patent number: D460914
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: July 30, 2002
    Assignee: Graham Packaging Company, L.P.
    Inventor: Sheldon E. Yourist