Patents Represented by Attorney James W. Judge
  • Patent number: 8323402
    Abstract: Methods of growing and manufacturing aluminum nitride crystal, and aluminum nitride crystal produced by the methods. Preventing sublimation of the starting substrate allows aluminum nitride crystal of excellent crystallinity to be grown at improved growth rates. The aluminum nitride crystal growth method includes the following steps. Initially, a laminar baseplate is prepared, furnished with a starting substrate having a major surface and a back side, a first layer formed on the back side, and a second layer formed on the first layer. Aluminum nitride crystal is then grown onto the major surface of the starting substrate by vapor deposition. The first layer is made of a substance that at the temperatures at which the aluminum nitride crystal is grown is less liable to sublimate than the starting substrate. The second layer is made of a substance whose thermal conductivity is higher than that of the first layer.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: December 4, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keisuke Tanizaki, Naho Mizuhara, Michimasa Miyanaga, Hideaki Nakahata, Yoshiyuki Yamamoto
  • Patent number: 8310030
    Abstract: Affords methods of manufacturing bulk III-nitride crystals whereby at least the surface dislocation density is low globally. The present III-nitride crystal manufacturing method includes: a step of preparing an undersubstrate (1) containing a III-nitride seed crystal, the III-nitride seed crystal having a matrix (1s), and inversion domains (1t) in which the polarity in the <0001> directions is inverted with respect to the matrix (1s); and a step of growing a III-nitride crystal (10) onto the matrix (1s) and inversion domains (it) of the undersubstrate (1) by a liquid-phase technique; and is characterized in that a first region (10s), being where the growth rate of III-nitride crystal (10) growing onto the matrix (1s) is greater, covers second regions (10t), being where the growth rate of III-nitride crystal (10) growing onto the inversion domains (1t) is lesser.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: November 13, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryu Hirota, Koji Uematsu, Tomohiro Kawase
  • Patent number: 8308878
    Abstract: Magnesium-based alloy wire excelling in strength and toughness, its method of manufacture, and springs in which the magnesium-based alloy wire is utilized are made available. The magnesium-based alloy wire contains, in mass %, 0.1 to 12.0% Al, and 0.1 to 1.0% Mn, and is provided with the following constitution. Diameter d that is 0.1 mm or more and 10.0 mm or less; length L that is 1000 d or more; tensile strength that is 250 MPa or more; necking-down rate that is 15% or more; and elongation that is 6% or more. Such wire is produced by draw-forming it at a working temperature of 50° C. or more, and by heating it to a temperature of 100° C. or more and 300° C. or less after the drawing process has been performed.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: November 13, 2012
    Assignees: Sumitomo Electric Industries, Ltd., Sumitomo (SEI) Steel Wire Corp.
    Inventors: Yukihiro Oishi, Nozomu Kawabe
  • Patent number: 8304334
    Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: November 6, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Patent number: 8293012
    Abstract: Affords AlxGa1-xN crystal growth methods, as well as AlxGa1-xN crystal substrates, wherein bulk, low-dislocation-density crystals are obtained. The AlxGa1-xN crystal (0<x?1) growth method is a method of growing, by a vapor-phase technique, an AlxGa1-xN crystal (10), characterized by forming, in the growing of the crystal, at least one pit (10p) having a plurality of facets (12) on the major growth plane (11) of the AlxGa1-xN crystal (10), and growing the AlxGa1-xN crystal (10) with the at least one pit (10p) being present, to reduce dislocations in the AlxGa1-xN crystal (10).
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: October 23, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Michimasa Miyanaga, Naho Mizuhara, Hideaki Nakahata
  • Patent number: 8294245
    Abstract: Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 10 has a wurtzitic crystalline structure and, at 30° C., its elastic constant C11 is from 348 GPa to 365 GPa and its elastic constant C13 is from 90 GPa to 98 GPa; alternatively its elastic constant C11 is from 352 GPa to 362 GPa.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: October 23, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideaki Nakahata, Shinsuke Fujiwara, Takashi Sakurada, Yoshiyuki Yamamoto, Seiji Nakahata, Tomoki Uemura
  • Patent number: 8258051
    Abstract: The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm), (10qm) of the designated plane orientation; a step of disposing the substrates (10p), (10q) adjoining each other sideways in such a way that the major surfaces (10pm), (10qm) of the substrates (10p), (10q) parallel each other and so that the [0001] directions in the substrates (10p), (10q) are oriented in the same way; and a step of growing III-nitride crystal (20) onto the major surfaces (10pm), (10qm) of the substrates (10p), (10q).
    Type: Grant
    Filed: May 17, 2009
    Date of Patent: September 4, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8227826
    Abstract: Affords a method of storing GaN substrates from which semiconductor devices of favorable properties can be manufactured, the stored substrates, and semiconductor devices and methods of manufacturing the semiconductor devices. In the GaN substrate storing method, a GaN substrate (1) is stored in an atmosphere having an oxygen concentration of 18 vol. % or less, and/or a water-vapor concentration of 12 g/m3 or less. Surface roughness Ra of a first principal face on, and roughness Ra of a second principal face on, the GaN substrate stored by the storing method are brought to no more than 20 nm and to no more than 20 ?m, respectively. In addition, the GaN substrates are rendered such that the principal faces form an off-axis angle with the (0001) plane of from 0.05° to 2° in the <1 100> direction, and from 0° to 1° in the <11 20> direction.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: July 24, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideyuki Ijiri, Seiji Nakahata
  • Patent number: 8134223
    Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: March 13, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Patent number: 8133815
    Abstract: Compound-semiconductor-substrate polishing methods, compound semiconductor substrates, compound-semiconductor-epitaxial-substrate manufacturing methods, and compound semiconductor epitaxial substrates whereby oxygen superficially present on the substrates reduced. A compound semiconductor-substrate polishing method includes a preparation step (S10), a first polishing step (S20), and a second polishing step (S30). In the preparation step (S10), a compound semiconductor substrate is prepared. In the first polishing step (S20), the compound semiconductor substrate is polished with a chloric polishing agent. In the second polishing step (S30), subsequent to the first polishing step (S20), a polishing operation utilizing an alkaline aqueous solution containing an inorganic builder and having pH of 8.5 to 13.0 inclusive is performed.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: March 13, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshio Mezaki, Takayuki Nishiura, Masahiro Nakayama
  • Patent number: 8110140
    Abstract: In methods of manufacturing optical components for infrared-light or ultraviolet-light applications, by lessening the expense consumed during finishing processes, a technique for manufacturing ceramic optical components inexpensively is realized. Raw material powders whose main constituent is ZnS, ZnSe or Ge, for ceramics for infrared-light optical components, and whose main constituent is CaF2 or MaF2, for ceramics for ultraviolet-light optical components, are molded into molded masses; the molded masses are sintered into sinters; and by pressing the sinters through a heating and compressing process, net-shape ceramic sinters can be produced. Alternatively, a finishing process is carried out after they are pressed into near-net shape. By shaping into net shape or near-net shape, the finishing process can be omitted, or the finishing process time and processing expense taken up can be decreased.
    Type: Grant
    Filed: December 25, 2002
    Date of Patent: February 7, 2012
    Assignee: Sumimoto Electric Industries, Ltd.
    Inventor: Masato Hasegawa
  • Patent number: 8012882
    Abstract: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, bow will be a large ±40 ?m to ±100 ?m. Since with that bow device fabrication by photolithography is challenging, reducing the bow to +30 ?m to ?20 ?m is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the bow. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the bow.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: September 6, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Naoki Matsumoto
  • Patent number: 8008173
    Abstract: A III nitride single-crystal manufacturing method in which a liquid layer (3) of 200 ?m or less thickness is formed in between a substrate (1) and a III nitride source-material baseplate (2), and III nitride single crystal (4) is grown onto the face (1s) on the liquid-layer side of the substrate (1). Herein, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side may be formed of a III nitride single crystal, while the III nitride source-material baseplate (2) can be formed of a III nitride polycrystal. Further, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side, and the III nitride source-material baseplate (2) can be formed of a III nitride single crystal, while the face (1s) on the liquid-layer side of the substrate (1) can be made a III-atom surface, and the face (2s) on the liquid-layer side of the III nitride source-material baseplate (2) can be made a nitrogen-atom surface.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: August 30, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Seiji Nakahata
  • Patent number: 8002892
    Abstract: Affords a Group-III nitride crystal substrate that is of low dislocation density and is inexpensive to manufacture, a method of manufacturing such a substrate, and Group-III nitride semiconductor devices that incorporate the Group-III nitride crystal substrate. The Group-III nitride crystal substrate manufacturing method includes: a step of growing, by liquid-phase epitaxy, a first Group-III nitride crystal (2) onto a base substrate (1); and a step of growing, by vapor-phase epitaxy, a second Group-III nitride crystal (3) onto the first Group-III nitride crystal (2). The Group-III nitride crystal substrate, produced by such a manufacturing method, has a dislocation density of 1×107 dislocations/cm2.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: August 23, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryu Hirota, Seiji Nakahata, Masaki Ueno
  • Patent number: 7998847
    Abstract: Affords methods of manufacturing bulk III-nitride crystals whereby at least the surface dislocation density is low globally. The present III-nitride crystal manufacturing method includes: a step of preparing an undersubstrate (1) containing a III-nitride seed crystal, the III-nitride seed crystal having a matrix (1s), and inversion domains (1t) in which the polarity in the <0001> directions is inverted with respect to the matrix (1s); and a step of growing a III-nitride crystal (10) onto the matrix (1s) and inversion domains (1t) of the undersubstrate (1) by a liquid-phase technique; and is characterized in that a first region (10s), being where the growth rate of III-nitride crystal (10) growing onto the matrix (1s) is greater, covers second regions (10t), being where the growth rate of III-nitride crystal (10) growing onto the inversion domains (1t) is lesser.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: August 16, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryu Hirota, Koji Uematsu, Tomohiro Kawase
  • Patent number: 7995267
    Abstract: Affords a wavelength converter manufacturing method and a wavelength converter whereby the transmissivity can be improved. A method of manufacturing a wavelength converter (10a) is provided with the following steps. At first, crystal is grown. Then a first crystal (11) and a second crystal (12) are formed by sectioning the crystal into two or more in such a way that the domains are the reverse of each other. The first and second crystals (11) and (12) are then interlocked in such a way that a domain inversion structure in which the polar directions of the first and second crystals (11) and (12) periodically reverse along an optical waveguide (13) is formed, and the domain inversion structure satisfies quasi-phase-matching conditions for an incoming beam (101).
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: August 9, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Issei Satoh, Michimasa Miyanaga, Yoshiyuki Yamamoto, Hideaki Nakahata
  • Patent number: 7991191
    Abstract: Clustering-definition-based encoding schemes printed as a computer-oriented digital layer onto a physical surface whereby the surface functions as an interface enabling, via a simple image-acquisition device scanning a minimal field required to establish the clustering definition, the provision, to a suitable data processing and human-oriented display means, of feedback on the orientation of the image-acquisition device relative to the digital layer overall.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: August 2, 2011
    Assignees: Sires Ltd.
    Inventors: Kamen Kanev, Shigeo Kimura
  • Patent number: 7964477
    Abstract: Affords III-nitride crystals having a major surface whose variance in crystallographic plane orientation with respect to an {hkil} plane chosen exclusive of the {0001} form is minimal. A method of manufacturing the III-nitride crystal is one of: conditioning a plurality of crystal plates (10) in which the deviation in crystallographic plane orientation in any given point on the major face (10m) of the crystal plates (10), with respect to an {hkil} plane chosen exclusive of the {0001} form, is not greater than 0.5°; arranging the plurality of crystal plates (10) in a manner such that the plane-orientation deviation, with respect to the {hkil} plane, in any given point on the major-face (10m) collective surface (10a) of the plurality of crystal plates (10) will be not greater than 0.5°, and such that at least a portion of the major face (10m) of the crystal plates (10) is exposed; and growing second III-nitride crystal (20) onto the exposed areas of the major faces (10m) of the plurality of crystal plates (10).
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: June 21, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Shinsuke Fujiwara
  • Patent number: 7960284
    Abstract: Affords a III-V compound semiconductor substrate manufacturing method that enables enhancement of the substrate PL intensity. In such a III-V compound semiconductor substrate manufacturing method, first, the surface 3a of a wafer 3 is polished (polishing step). Second, the surface 3a of the wafer 3 is cleaned (first cleaning step S7). Next, the surface 3a of the wafer 3 is subjected to first dry-etching, employing a halogen-containing gas, while first bias voltage is applied to a chuck 24 for carrying the wafer 3. Subsequently, the surface 3a of the wafer 3 is subjected to second dry-etching, employing the halogen-containing gas (second dry-etching step S11), while second bias power lower than the first bias power is applied to the chuck 24.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: June 14, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akihiro Hachigo, Naoki Matsumoto, Takayuki Nishiura
  • Patent number: 7892513
    Abstract: Affords group III nitride crystal growth methods enabling crystal to be grown in bulk by a liquid-phase technique. One such method of growing group III nitride crystal from solution is provided with: a step of preparing a substrate having a principal face and including at least on its principal-face side a group III nitride seed crystal having the same chemical composition as the group III nitride crystal, and whose average density of threading dislocations along the principal face being 5×106 cm?2 or less; and a step of bringing into contact with the principal face of the substrate a solution in which a nitrogen-containing gas is dissolved into a group III metal-containing solvent, to grow group III nitride crystal onto the principal face.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: February 22, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinsuke Fujiwara, Hiroaki Yoshida, Ryu Hirota, Koji Uematsu, Haruko Tanaka