Patents Represented by Attorney James W. Judge
  • Patent number: 7884393
    Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor (11) is provided with a supporting substrate (13) composed of gallium nitride, a buffer layer (15) composed of a first gallium nitride semiconductor, a channel layer (17) composed of a second gallium nitride semiconductor, a semiconductor layer (19) composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode (21), a source electrode (23) and a drain electrode (25) for the transistor (11). The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: February 8, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
  • Patent number: 7884351
    Abstract: In a nitride semiconductor light-emitting device (11), an emission region (17) has a quantum well structure (19), and lies between an n-type gallium nitride semiconductor region (13) and a p-type gallium nitride semiconductor region (15). The quantum well structure (19) includes a plurality of first well layers (21) composed of InxGa1-xN, one or a plurality of second well layers (23) composed of InyGa1-yN, and barrier layers (25). The first and second well layers (21) and (23) are arranged in alternation with the barrier layers (25). The second well layers (23) lie between the first well layers (21) and the p-type gallium nitride semiconductor region (15). The indium component y of the second well layers (23) is smaller than indium component x of the first well layers (21), and the thickness DW2 of the second well layers (23) is greater than the thickness DW1 of the first well layers (21).
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: February 8, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Katsushi Akita, Yusuke Yoshizumi
  • Patent number: 7872285
    Abstract: Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm?3 or more. The donor impurity is at least either silicon or germanium.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: January 18, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Makoto Kiyama, Tatsuya Tanabe, Kouhei Miura, Takashi Sakurada
  • Patent number: 7863167
    Abstract: Made available is a Group III nitride crystal manufacturing method whereby incidence of cracking in the III-nitride crystal when the III-nitride substrate is removed is kept to a minimum. III nitride crystal manufacturing method provided with: a step of growing, onto one principal face (10m) of a III-nitride substrate (10), III-nitride crystal (20) at least either whose constituent-atom type and ratios, or whose dopant type and concentration, differ from those of the III-nitride substrate (10); and a step of removing the III-nitride substrate (10) by vapor-phase etching.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: January 4, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Fumitaka Sato, Seiji Nakahata
  • Patent number: 7855569
    Abstract: The invention provides a wafer-prober wafer holder that allows positional precision and temperature uniformity to be increased, and also allows the chip to be heated and cooled rapidly, and a wafer prober device provided with the same. The wafer-prober wafer holder of the invention is constituted by a chuck top having a chuck top conducting layer on its surface, and a support member for supporting the chuck top, and has a cavity in a portion between the chuck top and the support member. The chuck top preferably is provided with a heating member.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: December 21, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masuhiro Natsuhara, Katsuhiro Itakura, Hirohiko Nakata
  • Patent number: 7811908
    Abstract: Affords a method of storing GaN substrates from which semiconductor devices of favorable properties can be manufactured, the stored substrates, and semiconductor devices and methods of manufacturing the semiconductor devices. In the GaN substrate storing method, a GaN substrate (1) is stored in an atmosphere having an oxygen concentration of 18 vol. % or less, and/or a water-vapor concentration of 12 g/m3 or less. Surface roughness Ra of a first principal face on, and roughness Ra of a second principal face on, the GaN substrate stored by the storing method are brought to no more than 20 nm and to no more than 20 ?m, respectively. In addition, the GaN substrates are rendered such that the principal faces form an off-axis angle with the (0001) plane of from 0.05° to 2° in the <1 100> direction, and from 0° to 1° in the <11 20> direction.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: October 12, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideyuki Ijiri, Seiji Nakahata
  • Patent number: 7781314
    Abstract: Affords a manufacturing method enabling nitride-based semiconductor devices containing epitaxial films excelling in flatness and crystallinity to be easily produced. Method of manufacturing nitride semiconductor devices that are formed onto a semiconductor substrate being a compound containing nitrogen, and a Group IIIA element for forming compounds with nitrogen, including steps of: heating the semiconductor substrate (1) to a film-deposition temperature; supplying to the substrate a film-deposition gas containing a source gas for the Group IIIA element and a nitrogen source gas; and epitaxially growing onto the semiconductor substrate a thin film (2) of a compound containing nitrogen and the Group IIIA element; and being furnished with a step, in advance of the epitaxial growth step, of heating the semiconductor substrate to a pretreating temperature less than the film-deposition temperature, to clean the surface of the semiconductor substrate.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: August 24, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Masaki Ueno
  • Patent number: 7763892
    Abstract: Affords a Group III nitride semiconductor device having a structure that can improve the breakdown voltage. A Schottky diode (11) consists of a Group III nitride support substrate (13), a gallium nitride region (15), and a Schottky electrode (17). The Group III nitride support substrate (13) has electrical conductivity. The Schottky electrode (17) forms a Schottky junction on the gallium nitride region (15). The gallium nitride region (15) is fabricated on a principal face (13a) of the Group III nitride support substrate (13). The gallium nitride region (15) has a (10 12)-plane XRD full-width-at-half-maximum of 100 sec or less.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: July 27, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kouhei Miura, Makoto Kiyama, Takashi Sakurada
  • Patent number: 7749828
    Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: July 6, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
  • Patent number: 7732236
    Abstract: The invention provides Group III nitride semiconductor crystals of a size appropriate for semiconductor devices and methods for manufacturing the same, Group III nitride semiconductor devices and methods for manufacturing the same, and light-emitting appliances. A method of manufacturing a Group III nitride semiconductor crystal includes a process of growing at least one Group III nitride semiconductor crystal substrate on a starting substrate, a process of growing at least one Group III nitride semiconductor crystal layer on the Group III nitride semiconductor crystal substrate, and a process of separating a Group III nitride semiconductor crystal, constituted by the Group III nitride semiconductor crystal substrate and the Group III nitride semiconductor crystal layer, from the starting substrate, and is characterized in that the Group III nitride semiconductor crystal is 10 ?m or more but 600 ?m or less in thickness, and is 0.2 mm or more but 50 mm or less in width.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: June 8, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Hideaki Nakahata, Koji Uematsu, Makoto Kiyama, Youichi Nagai, Takao Nakamura
  • Patent number: 7732066
    Abstract: Surface-coated machining tools in particular utilized in routing, slitting and drilling processes on printed circuit boards onto which integrated circuits and various electronic parts are populated. A cemented-carbide base material containing tungsten carbide and cobalt, with the cobalt inclusion amount being 4 weight % or more and 12 weight % or less, is furnished. A compound thin film made up of a combination of one or more elements selected from the group titanium, chromium, vanadium, silicon and aluminum, and one or more selected from carbon and nitrogen, is coated over the cemented-carbide base material. The compound thin film is coated in at least a single layer.
    Type: Grant
    Filed: December 8, 2002
    Date of Patent: June 8, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Haruyo Fukui, Tatsuro Fukuda
  • Patent number: 7723248
    Abstract: Highly wear-resistant, low-friction ceramic composites suited for machining-tool, sliding-component, and mold-die materials are made available. The ceramic composites characterized are constituted from a phase having carbon of 3 ?m or less, preferably 30 nm or less, average crystal-grain size as the principal component, and a ceramic phase (with the proviso that carbon is excluded). The ceramic phase is at least one selected from the group made up of nitrides, carbides, oxides, composite nitrides, composite carbides, composite oxides, carbonitrides, oxynitrides, oxycarbonitrides, and oxycarbides of Al, Si, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo and W. The ceramic composites are produced by sintering the source-material powders at a sintering temperature of 800 to 1500° C. and a sintering pressure of 200 MPa or greater.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: May 25, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomoyuki Ueno, Masashi Yoshimura
  • Patent number: 7622225
    Abstract: Affords for lithium secondary batteries a negative electrode component material that enhances battery cyclability by inhibiting dendritic growth that occurs during charging/discharging due to the reaction of the metallic lithium and organic electrolyte. A substrate for a lithium-secondary-battery negative-electrode component material (5), in which a metallic lithium film (3) is formed atop the substrate and onto the metallic lithium film an inorganic solid electrolytic film (4) is formed, is created from an electrical insulator that can be a polyethylene film (1). A configuration providing an electrically insulating layer at the interface between a metal base material and the metallic lithium film may also be utilized as the substrate.
    Type: Grant
    Filed: May 31, 2004
    Date of Patent: November 24, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Nobuhiro Ota, Nobuyuki Okuda, Hiroyuki Ueki, Tomohiko Ihara
  • Patent number: 7573638
    Abstract: Practical diffractive optical elements are made available efficiently and at low-cost. A refractive-index-modulated diffractive optical element includes a transparent DLC (diamond-like carbon) film (2) formed on a transparent substrate (1), with the DLC film (2) containing a diffraction grating having local regions (2a) of a relatively high refractive index and local regions (2) of a relatively low refractive index. The DLC film (2) can readily be deposited by plasma CVD onto the substrate (1), and the high refractive-index regions (2a) within the DLC film can readily be formed by irradiating it with an energy beam (4) such as an ion beam.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: August 11, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toshihiko Ushiro, Soichiro Okubo, Takashi Matsuura
  • Patent number: 7554175
    Abstract: Fracture-resistant gallium nitride substrate, and methods of testing for and manufacturing such substrates are made available. A gallium nitride substrate (10) is provided with a front side (12) polished to a mirrorlike finish, a back side (14) on the substrate side that is the opposite of the front side (12). A damaged layer (16) whose thickness d is 30 ?m or less is formed on the back side (14). Given that the strength of the front side (12) is I1 and the strength of the back side (14) is I2, then the ratio I2/I1 is 0.46 or more.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: June 30, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Akihiro Hachigo
  • Patent number: 7547910
    Abstract: Affords a semiconductor light-emitting device in which a decrease in external quantum efficiency has been minimized even at high current densities. In a semiconductor light-emitting device (11), a gallium nitride cladding layer (13) has a threading dislocation density of 1×107 cm?2 or less. An active region (17) has a quantum well structure (17a) consisted of a plurality of well layers (19) and a plurality of barrier layers (21), and the quantum well structure (17a) is provided so as to emit light having a peak wavelength within the wavelength range of 420 nm to 490 nm inclusive. The well layers (19) each include an un-doped InXGa1-XN (0<X<0.14, X: strained composition) region. The barrier layers (21) include an un-doped InYGa1-YN (0?Y?0.05, Y: strained composition, Y<X) region. Herein, indium composition X is indicated as strained composition, not as relaxation composition, in the embodiments of the present invention.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: June 16, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Yusuke Yoshizumi, Takashi Kyono, Hiroyuki Kitabayashi, Koji Katayama
  • Patent number: 7534295
    Abstract: A III nitride single-crystal manufacturing method in which a liquid layer (3) of 200 ?m or less thickness is formed in between a substrate (1) and a III nitride source-material baseplate (2), and III nitride single crystal (4) is grown onto the face (1s) on the liquid-layer side of the substrate (1). Herein, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side may be formed of a III nitride single crystal, while the III nitride source-material baseplate (2) can be formed of a III nitride polycrystal. Further, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side, and the III nitride source-material baseplate (2) can be formed of a III nitride single crystal, while the face (1s) on the liquid-layer side of the substrate (1) can be made a III-atom surface, and the face (2s) on the liquid-layer side of the III nitride source-material baseplate (2) can be made a nitrogen-atom surface.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: May 19, 2009
    Assignee: Sumitomo Electric Industries, Ltd
    Inventor: Seiji Nakahata
  • Patent number: 7518216
    Abstract: A method of forming an iron-doped gallium nitride for a semi-insulating GaN substrate is provided. A substrate 1, such as a sapphire substrate having the (0001) plane, is placed on a susceptor of a metalorganic hydrogen chloride vapor phase apparatus 11. Next, gaseous iron compound GFe from a source 13 for an iron compound, such as ferrocene, and hydrogen chloride gas G1HCl from a hydrogen chloride source 15 are caused to react with each other in a mixing container 16 to generate gas GFeComp of an iron-containing reaction product, such as iron chloride (FeCl2). In association with the generation, the iron-containing reaction product GFeComp, first substance gas GN containing elemental nitrogen from a nitrogen source 17, and second substance gas GGa containing elemental gallium are supplied to a reaction tube 21 to form iron-doped gallium nitride 23 on the substrate 1.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: April 14, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akinori Koukitu, Yoshinao Kumagai, Yoshiki Miura, Kikurou Takemoto, Fumitaka Sato
  • Patent number: 7491432
    Abstract: For semiconductor manufacturing equipment, a ceramic susceptor that without occurrence of cracking in the course of heating wafers suppresses thermal radiation from the circumferential surface of a wafer placed on the ceramic susceptor, to heighten isothermal quality in the wafer face. A semiconductor-manufacturing-equipment ceramic susceptor (1) including a resistive heating element (3) in the face or interior of ceramic substrates (2a, 2b) has a wafer pocket (5) consisting of a recess that can accommodatingly carry a wafer. The angle that the perimetric inside surface and the bottom face of the wafer pocket (5) form is over 90° and 170° or less, and/or the curvature of the bottom-portion circumferential rim where the perimetric inside surface and the bottom face of the pocket join is 0.1 mm or more. A plasma electrode furthermore may be disposed in the face or interior of the ceramic substrates (2a, 2b) of the ceramic susceptor (1).
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: February 17, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshifumi Kachi, Akira Kuibira, Hirohiko Nakata
  • Patent number: 7485484
    Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. The III-V crystals are obtained by manufacturing method characterized in including: a step of depositing a metal film (2) on a substrate (1); a step of heat-treating the metal film (2) in an atmosphere in which a patterning compound is present; and a step of growing a group III-V crystal (4) on the metal film after the heat treatment. Alternatively, the III-V crystal manufacturing method is characterized in including: a step of growing a group III-V compound buffer film on the metal film after the heat treatment; and a step of growing a group III-V crystal on the group III-V compound buffer film.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: February 3, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota