Abstract: An aerospace hardware derelict item is salvaged in space, modified, and reused to provide manned facilities in orbit. The hardware packages added onto the salvaged discarded item enhances its value, and incorporates at least the subsystems required to effectively reuse portions of previously discarded launch vehicle components, and other derelict objects in space. The hardware, and technique used reduces the cost of launching comparable hardware to orbit, because of the reuse, and provides a human habitation in orbit. The salvaged items include the external tank of the space shuttle, other derelict orbital hardware, the add-on cargo pod in two forms, and the ability to convert the derelict into a cost effective reusable item. The salvaged hardware is initially capable of contributing mass, length, interior volume, strongback, rotational stability mass, interior pressurized volumes, artificial gravity, and stability with the addition of simple subsystems for salvage, and interior development packages.

Abstract: A semiconductor device for mounting on an external substrate includes a semiconductor chip, a high thermal elastic internal substrate and a high elastic liquid resin. The semiconductor chip has bump electrodes formed on its main surface. The high thermal elastic internal substrate includes a conductive pattern on one surface and external electrodes on the other surface. The conductive pattern is electrically connected to the bump electrodes. The external electrodes are electrically connected to the conductive pattern and mounted on the external substrate. The high elastic liquid resin covers the surface of the semiconductor chip, the one surface of the internal substrate and the bump electrodes. The internal substrate has a Young modulus of about 8000 to 15000 kg/mm2, which is larger than a Young modulus of the external substrate.

Abstract: There is provided a monitoring system for monitoring semiconductor device fabrication facilities by allocating a specific frequency on each of the semiconductor device fabrication facilities, and connecting between each of the facilities and a central monitoring apparatus with information transmission line and selective signal line thereby simplifying the monitoring lines.

Abstract: A method for ashing a resist pattern covered by a hardened layer caused by an ion implantation process previously conducted including a first step for conducting an ashing process at a first temperature e.g. 129° C. or less at which no popping phenomenon happens, for removing the hardened layer, and a second step for conducting an ashing process at a second temperature e.g. 150° C. at which the ashing rate is high, for entirely removing the remaining resist pattern, and apparatus employable for the method for ashing a resist pattern covered by a hardened layer including a mechanism for moving up and down a semiconductor wafer to regulate the temperature of the semiconductor wafer and including a shutter which intervenes between the semiconductor wafer and a heater.

Abstract: The invention typically relates to a semiconductor device comprising a driving portion composed of an output transistor NMOS 130 or PMOS 129 for driving an output terminal, and a control portion for controlling the operation state of the driving portion. The control portion outputs an enable signal for turning on or off the output transistor NMOS 130 or PMOS 129. The enable signal is produced by a pulse-shaped read instruction signal IN1 for increasing the time involved in the change from on to off of the output transistor NMOS 130 or PMOS 129.

Abstract: A circulation system for supplying one or more chemicals, or mixtures thereof, includes a chemical tank containing the chemical. A chemical supply line is connected at one end to the chemical tank, through which the chemical from the chemical tank is supplied to one of a processing section, for performing a specific semiconductor device fabrication process, and a bypass section, for collecting the chemical while the processing section is idle. A supply nozzle, connected to another end of the chemical supply line, is movable between the processing section and the bypass section, such that the supply nozzle is selectively oriented above one of the processing section and the bypass section. A primary chemical re-circulation line connects the processing section and the chemical tank, and a chemical bypass line connects the bypass section and a portion of the primary chemical re-circulation line.

Abstract: A method for forming a self-aligned contact includes forming a second insulating layer, on a first insulating layer including a first self-aligned contact pad formed on a semiconductor substrate, forming a conductive architecture on the second insulating layer, and forming a second self-aligned contact pad on both sides of the conductive architecture. The conductive architecture is covered with a material layer having an etch selectivity with respect to the second insulating layer and the second self-aligned contact pad is electrically connected to the first self-aligned contact pad. Thus, a self-aligned contact pad is formed with two layers. Accordingly, the contact is self-aligned to a gate electrode and a bit line, thereby preventing shorts generated by misalignment. Further, the etching thickness is reduced while etching an oxide layer to form a storage node contact hole, thereby suppressing shorts and reducing the critical dimension of a storage node contact.

Abstract: The presence of particles on the wafer holder of semiconductor exposure equipment is detected by analyzing any up-and-down movement of the stage during the alignment, for exposure, of a wafer mounted on the wafer holder. The analysis of the up-and-down movement of the stage is conducted based on signals from a motor which moves the stage in the vertical (Z-axis) direction, or based on signals from a sensor indicative of the distance that the stage deviates vertically from a reference position. A feedback mechanism produces information representative of the up-and-down movement of the stage, and a computer processes the signals to produce data indicative of whether particles are present beneath the wafer on the stage.

Abstract: A method and apparatus for grinding wafers without using an ultraviolet tape attached to the front face of the wafer reduces manufacturing costs, simplifies the grinding process and protects the semiconductor chips formed on the front face of the wafer from being damaged by static electricity. The grinding apparatus uses a grind chuck formed of a soft material having a high elastic modulus and a rising groove formed in the grind chuck. Deionized water is supplied onto the wafer from a first direction. Simultaneously, deionized water or air is supplied into the rising groove of the grind chuck from a second direction opposite to the first direction. The circumferential edge of the wafer overlaps the rising groove, such that the simultaneous supply of deionized water and/or air from the two directions protects the front surface of the wafer from being contaminated by silicon dust.

Abstract: A module of a host computer of a semiconductor fabrication management system receives from an operator a plurality of IDs assigned by the operator to each of the wafers, respectively, received in the slots of a wafer cassette. The module searches a database of the host computer to correlate each received wafer ID with a process step ID, and the process step ID with a process program ID (PPID). Process condition data is formulated from the correlated process step IDs and PPIDs. At this point, the semiconductor fabrication management system is used to determine whether the operator has inputted a track-in signal to the system. If the track-in signal has been inputted, the processing condition data is downloaded to a server of the semiconductor processing equipment. The downloaded process condition data is used to change, if necessary, an equipment control message stored in the server.

Abstract: There is disclosed a method and apparatus for etching a substrate. The method comprises the steps of etching a substrate or alternately etching and depositing a passivation layer. A bias frequency, which may be pulsed, may be applied to the substrate and may be at or below the ion plasma frequency.

Abstract: A semiconductor memory device includes first through fourth memory blocks. A first block-selection signal is used to select the first and third memory blocks, to output data from the first memory block to the first data line and also to output data from the fourth memory block to the second data line. A second block-selection signal is used to select the second and third memory blocks, to output data from the second memory block to the second data line and also to output data from the third memory block to the first data line.

Abstract: A Platen, generally indicated at (10), comprises a ceramic body (11) and a workpiece support surface (12) and a base (13). Embodied within the body (11) are an electrostatic chuck electrode (40), an RF electrode (15), a heater (16), a ground plane electrode (17), an embedded thermocouple (18), and a stainless steel support (19). This combination provides a platen which can be RF driven, but has a screen to prevent unwanted plasma beneath the platen. The chuck can also be utilized as an electrostatic chuck.

Abstract: A method of fabricating a semiconductor device where the formation of a conductive layer typically over a storage capacitor on the device is used both as a plate electrode and also as an interconnect line. The method therefore combines the fabrication process steps of forming a plate electrode with the steps of forming a wiring layer. In a preferred embodiment, the storage capacitor is part of a cell array portion of a semiconductor memory device, whereas the interconnect line is in a peripheral portion of the memory device.

Abstract: An SRAM cell having a word line shorter than a bit line is provided. First and second driver transistors having first and second gate electrodes parallel to each other are formed on a semiconductor substrate, and a third gate electrode shared by first and second transfer transistors is formed between the first and the second gate electrodes. A word line electrically connected to the third electrode is perpendicular to the first and the second gate electrodes, and a pair of bit lines electrically connected to drain areas of the first and the second transfer transistors are perpendicular to the word line. Also, a pair of ground lines are electrically connected to the source areas of the first and the second driver transistors, and are parallel to the bit lines.

Abstract: An object of the present invention is to manufacture a semiconductor device excellent in withstand-voltage property of each element formed in a peripheral element region portion, without incurring complexity of a manufacturing process. Impurity ions are injected into a substrate so as to form a first well portion and field oxide films for partitioning a substrate surface including the surface of the first well portion into a plurality of active regions. Further, the impurity ions are injected into the first well portion so as to form a second well portion having a plurality of active regions. Regions corresponding to the active regions on the second well portion are exposed and a mask for covering regions other than the above regions is formed. Ions are injected into the second well portion exposed from the mask under the action of energy transmitted through the field oxide films.

Abstract: A dielectric window of a dry etching apparatus for manufacturing semiconductor devices is shaped so that areas of high density plasma in the etching apparatus correspond to portions of the dielectric window further away from the wafer and areas of lower density plasma correspond to portions of the dielectric window closer to the wafer. For example, the dielectric window may be curve inwards at its center in a concave-shape.

Abstract: This invention relates to sputtering materials onto workpieces. Sputter Apparatus which is generally indicated at 10, is provided with additional D.C. coils 23, 23, to increase uniformity of deposition.

Abstract: A method for controlling thicknesses of layers formed by a deposition apparatus for semiconductor device fabrication includes retrieving a latest process record for a latest batch from a process database for a deposition apparatus. Each process record in the database describes one layer deposition process using the deposition apparatus operating on one batch. A batch includes a plurality of lots, each lot having a workpiece. The method further includes receiving a latest array of thicknesses, each thickness from one lot of the latest batch. Then an automatic corrected setting is calculated. If the automatic corrected setting is within a specification setting range, the specification is met and the method continues. A next batch signal is input if the layer deposition process may proceed on a next batch, and the automatic corrected setting is displayed. A predetermined correction command is input to indicate a predetermined corrected setting is to be used instead of the automatic corrected setting.

Abstract: An ion implanter which prevents undesired impurities from being implanted into a wafer has an ion source for producing an ion beam which is to be implanted into a wafer, an accelerator for accelerating the ion beam, and an impurity interceptor for intercepting impurities generated in the accelerator. The impurity interceptor has an intercepting plate electrically connected to a high voltage power supply, and an opening formed in the center of the plate. Undesired ions having an energy lower than the high voltage applied to the intercepting plate are intercepted, and only those desired ions having an energy higher than the high voltage applied to the intercepting plate pass through the opening.