Abstract: A wafer holding stage used during a semiconductor device fabricating process decreases the number of particles that accumulate on a wafer. The wafer holding stage includes a stage having an upper surface for holding a wafer and a heating element disposed inside the stage for raising temperatures of the upper surface to a holding temperature above an ambient temperature. The heating element may be a heating wire for producing heat when supplied with a electric current or a heat exchange tube for carrying a heated fluid. The wafer holding stage may further comprise a low temperature particle collector, having a surface maintained at a collecting temperature below the ambient temperature, spaced apart a small distance from the stage.

Abstract: A photosensitive semiconductor device includes a photocoupler sealed within a sealing body which is composed of a light-transmissive resin material. An outer surface of the sealing body is carbonized to block external light and thus minimized the adverse effects of noise.

Abstract: According to the present invention, there is provided an oscillating circuit comprising: an gate circuit coupled between a first electrical source and a second electrical source, the gate circuit outputting an oscillating signal from an output terminal in response to the standby signal; an switch circuit having an one end and an other end, the one end coupled to the output terminal of the gate circuit and the second terminal, the other end coupled to the first terminal, the switch circuit electrically connecting or disconnecting the first terminal and the second terminal in response to the standby signal.

Abstract: An annular ring shaped baffle plate disposed between a process chamber and a vacuum chamber of a dry etching apparatus. A plurality of slits are formed radially along the annular ring and extend from a top surface of the annular ring to a bottom surface of the annular ring. The slits are circumferentially spaced from each other, and each of the slits has an upper section that is tapered and a lower section that has a constant width. Alternatively, the slits may be replaced by a plurality of discharging regions formed in the annular ring, with the discharging regions having a circumferential width that is greater than a radial length.

Abstract: A method and system for transferring a wafer cassette between an Automated Guide Vehicle (AGV) and process equipment in a semiconductor fabrication facility involves transmitting a first signal from the AGV to the process equipment indicative of a cassette transfer request, checking whether the process equipment is in a suitable mode, setting the process equipment to the suitable mode after the checking step if the process equipment was not already in the suitable mode, and transferring the cassette between the AGV and the process equipment. A second transmitting step may be included, which sends a signal from the process equipment to the AGV authorizing the transfer of the cassette. The transmissions may be accomplished by wireless communications links such as a photo-coupled Parallel Input/Output link. A plurality of sensors may be used to detect whether a cassette is anywhere on a cassette stage during the checking step.

Abstract: A semiconductor device having a multilayer structure and a method of manufacturing the semiconductor device are disclosed. The semiconductor device according to the present invention has a semiconductor element including pad electrodes formed on the electrode area thereof, a first insulation layer formed on the circuit formation area of the semiconductor element, and a first circuit pattern formed on said first insulation layer. The first circuit pattern electrically connected to the pad electrodes. The semiconductor device of the present invention further has a second insulation layer formed on the first circuit pattern including a first through hole for exposing the first circuit pattern, and a second circuit pattern formed on the second insulation layer. The second circuit pattern is electrically connected to the pad electrodes and has a second through hole for exposing the first circuit pattern.

Abstract: A semiconductor package is includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with a elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the substrate and with its electrode being aligned within the elongate opening. The electrode of the semiconductor chip is electrically connected to the connecting pattern via wires elongate opening the through. The elongate opening and the wires are sealed with resin.

Abstract: This invention relates to methods of forming a barrier layer including depositing a layer of Titanium Nitride and subsequently nitriding the surface of that layer. In some embodiments the Titanium Nitride layer is exposed to Oxygen prior to the nitroding step.

Abstract: An oscillation circuit includes an oscillation terminal, and an inverter which is coupled to the oscillation terminal and which outputs an oscillation signal according to a resonant frequency of a resonator to be connected to the oscillation terminal. The oscillation circuit also includes resistors having different resistance values, and a select circuit which sequentially operatively connects the resistors between the inverter and a voltage source in response to the oscillation signal.

Abstract: A wafer packaging method in which a wafer is placed into a packaging bag that is sealed before the concentration of sulphuric oxide on the surface of the wafer reaches 3×1012 atoms/cm2.

Abstract: Signals inputted from nodes N2 and N4 to output circuit 100 are respectively transmitted to clocked inverters 31 and 32. Clocked inverter 31 is activated when node N4 is H level while clocked inverter 32 is activated when node N2 is L level. Output signal of clocked inverter 31 is supplied to gate electrode of PMOS 61 via node N5 while output signal of clocked inverter 32 is supplied to gate electrode of NMOS 62 via node N6. Voltage level of node N5 is pulled up when node N4 is L level while voltage level of node N6 is pulled down when node N2 is H level. With such a construction, it is possible to provide the output circuit capable of reducing feedthrough current without deteriorating high speed responsivity.

Abstract: The present invention provides a grinding apparatus for semiconductor wafers for preventing the silicon powder generated from the wafer grinding process and mixed with cooling water from contaminating height gauges of the grinding apparatus because the silicon powder is scattered toward them, and for preventing wear-down of the contact heads of the height gauges due to the abrasion with a wafer to be fixed on a spin-chuck and the spin-chuck.

Abstract: A dissolution inhibitor for use in a chemically amplified photoresist, and a chemically amplified photoresist composition containing the same are provided. The dissolution inhibitor is a compound in which an acid-labile di-alkylmalonate group is combined as a functional group with a C.sub.1 to C.sub.20 hydrocarbon. The chemically amplified photoresist composition containing the dissolution inhibitor has a high contrast and high thermal decomposition temperature, making it suitable for forming a fine pattern having excellent profile.

Abstract: A polishing pad used for the chemical mechanical polishing (CMP) of a semiconductor substrate includes a polishing surface having at least first and second discrete polishing regions effecting differing amounts of polishing. Each polishing region includes at least one opening which holds the slurry that effects the chemical polishing of the substrate, and a contact surface left around the at least one opening which effects the mechanical polishing. The second polishing region has a ratio of the volume of the openings thereof with respect to unit area of the region which is different from the ratio of the volume of the openings of the first polishing region with respect to unit area of the first polishing region.

Abstract: In the present invention, a precharge circuit includes a precharge supply for setting equal potentials at pairs of spaced signal lines extending in parallel with respect to each other, a pair of switching elements for connecting and disconnecting respective signal lines to the supply, and a short circuit switching element for connecting and disconnecting short circuiting of the signal lines. The short circuit switching element consists of a transistor comprising a source and drain constituted by a pair of impurity regions formed underneath the pair of signal lines so as to correspond to the pair of signal lines and a gate. The gate of the transistor is formed in such a manner that gate length coincides with the widthwise direction of the pair of signal lines.

Abstract: A nonvolatile semiconductor device which includes a word line, a bit line, and a memory cell connected to the word line and the bit line, also has a word line driving circuit for driving the word line with a word line voltage supplied in response to a shut off signal in accordance with each mode of operation, and a circuit for generating the shut off signal during each mode of operation. The circuit generates the shut off signal which has a power supply voltage when the word line voltage is higher than the power supply voltage, and has the word line voltage when the word line voltage is less than the power supply voltage.

Abstract: An output circuit of a semiconductor memory device is made up of a level recognition circuit which outputs a feedback signal by comparing an output node and a second reference voltage, and a P-channel MOS transistor and an N-channel MOS transistor which complimentary turn on and off in response to the feedback signal. As a result, when a charge of the output node is not sufficient, the output node is charged by setting a voltage of a power supply node to a power supply voltage Vcc. Then, when the output node is sufficiently charged, the N-channel MOS transistor turns on, and as a result the voltage of the power supply node is set to a first reference voltage. Accordingly, the output circuit of the semiconductor memory device achieves an increased operation speed and decreased voltage level amplitude at the output node.

Abstract: A semiconductor device includes a semiconductor substrate having a major surface, a source region of a second conductivity type, a drain region of the second conductivity type, and a first insulating layer formed over the major surface between the source region and the drain region. The device also includes a control electrode layer formed over the first insulating layer and a second insulating layer formed over the major surface. The device also includes a first wiring layer formed in the first contact hole and a second wiring layer formed in the second contact hole and connected to a pad and an internal circuitry, wherein the internal circuitry executes a predetermined operation and wherein the pad receives a signal from the internal circuitry or a signal from an external device.

Abstract: A method of manufacturing thin films formed from multi-element group oxide includes supplying precursors containing elements later forming an oxide layer into a reaction chamber containing a semiconductor substrate on which an under-layer is formed, reacting an oxidizing gas supplied into the reaction chamber with the precursors to form the oxide layer on the under-layer, and supplying an organic ligand into the reaction chamber to improve planarity of the surface of the oxide layer.

Abstract: An object of the present invention is to provide a method of manufacturing a semiconductor device, which is capable of reducing metal-film stress produced upon formation of a high melting-point metal film by Chemical Vapor Deposition (CVD) and is very good in controllability. A typical invention of the present application is intended for the implantation of ions of an inert gas in the high melting-point metal film after deposition of the high melting-point metal film over a semiconductor wafer by CVD. According to the typical invention of the present application, since warpage of the semiconductor wafer due to the high melting-point metal film can be reduced, a failure in focus can be reduced in a patterning process for forming the subsequent interconnections, particularly an exposure process using a stepper. Accordingly, interconnections having desired dimensions can be formed.