Abstract: An apparatus for transferring a wafer carrier is capable of recognizing both a bar code of the wafer carrier and a vision mark for position correction attached to a processing equipment. It is possible to recognize both the bar code and the vision mark using a single image recognition device, by determining a required focal length for a lens in the image recognition device, and by determining the required size of the vision mark. Therefore, a separate bar code reader to recognize the bar code is not required in the processing equipment. This results in a reduced cost and increased productivity, since the processing equipment need not to be shut down for installation of a bar code reader.

Abstract: A trench isolation method is provided that prevents the formation of a dent between a trench isolation region and an active region and prevents the generation of water spots during a cleaning process. In the trench isolation method, an undercut is formed in a stress-relief oxide pad pattern formed below a nitride layer pattern that defines an active region as a mask pattern. A nitride liner, which is a stress-buffer layer, is then formed around the undercut such that is conforms to the shape of the undercut. Thus, even though the stress-buffer layer is partially etched during the removal of the nitride the hard mask pattern, the stress-buffer layer is not etched to a position below the upper surface of the substrate. Also, an anti-reflection layer, which is the main source of water spots, is simultaneously removed in the formation of the undercut.

Abstract: A thinner composition for removing photoresist, a rework method for wafers, and a method of manufacturing semiconductor devices are provided. The thinner composition is applied for removing excess photoresist coated on the edge side or back side of wafer. The thinner may be a mixture of ethyl lactate (EL), ethyl-3-ethoxy propionate (EEP), and .tau.-butyro lactone (GBL), or a mixture of ethyl lactate (EL), and ethyl-3-ethoxy propionate (EEP), or a mixture of ethyl lactate (EL), and ethyl-3-ethoxy propionate (EEP). The rework process is carried out, using the above thinner compositions, on the wafers having excess coated photoresist due to an etching failure. The method of manufacturing semiconductor devices includes a rinsing step for removing the excess coated photoresist on the edge side or back side of wafer by using the above thinner compositions.

Abstract: A semiconductor diode device having the characteristic of soft recovery and a method for manufacturing the same. A first N+ layer contacts with a cathode electrode. An N- epitaxial layer is formed on the first N+ layer. A P- layer is formed to have an undulating junction with the N- epitaxial layer. A second N+ layer is embedded in the P- layer. An anode electrode is attached to the P- layer, wherein the anode contact to the P- layer includes the second N+ layer. A channel stop region and insulating layer are also added to the structure.

Abstract: Circuitry capable of controlling a bias voltage for an avalanche photodiode (APD) in accordance with the temperature slope of the breakdown voltage of the APD is disclosed. A reference voltage generating circuit sets a voltage implementing an optimal amplification ratio on an output terminal, and generates a reference voltage by taking account of the temperature slope of the breakdown voltage of the APD. The reference voltage is applied to one input of a voltage comparator. A setting circuit feeds to an adding circuit a preselected voltage for controlling the voltage on the output terminal to a value capable of implementing the optimal multiplication ratio. A temperature compensating circuit feeds to the adding circuit a voltage corresponding to the temperature slope of the above breakdown voltage. The temperature slope is representative of the variation of the breakdown voltage with respect to temperature.

Abstract: A method of forming self-aligned contact holes of a semiconductor device presents bridging from occurring between contacts formed in the holes. First, gate electrode structures are formed on a semiconductor substrate. Next, an interlayer insulating film is formed over the gate electrode structures. The interlayer insulating film is formed by forming a first oxide layer of a reflowable material over the semiconductor substrate and gate electrode structures, planarization etching the first oxide layer until the upper portions of the gate electrode structures are uncovered, and then forming a second oxide layer on the planarized upper surface of the first oxide layer. The second oxide layer is selected to have a wet etch rate that is lower than that of the first oxide layer. Then, the insulating film is etched to form a contact hole between gate electrode structures.

Abstract: A capacitor in a semiconductor device is constituted by a lower electrode having a laminated layer including an adhesive layer formed on an insulating film, a barrier layer formed so as to cover the upper surface of the insulating layer, a nitride side formed so as to cover the side face of the adhesive layer, and an electrode layer formed so as to cover the upper surface of the barrier layer, a capacitor insulating film formed so as to cover the upper surface and side surface of the lower electrode, and an upper electrode formed so as to cover the surface of the capacitor insulating film.

Abstract: In an amplifier having an input terminal to which input data is supplied and an output terminal from which output data corresponding to the input data is output, the input and output terminals are disposed between a power supply node to which a power supply is applied and a reference voltage node to which a reference voltage is applied. The output terminal and the reference voltage node are connected to each other and the input terminal and the output terminal are disconnected from each other, before the input data is supplied to the input terminal. The output terminal and the reference voltage node are disconnected from each other and the input terminal and the output terminal are connected to each other, after the input data is supplied to the input terminal.

Abstract: A wafer cleaning process using standard cleaning 1 (SC1) solution includes a step of supplementing the cleaning solution with predetermined amounts of NH.sub.4 OH and H.sub.2 O.sub.2, or NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O during the cleaning of wafers with the solution so that a constant composition of the solution is maintained. After the cleaning solution is replaced with a fresh one, the solution is stabilized for a certain period of time to accomplish a complete mixing of the components therein. The present invention prolongs the useful life of standard cleaning solution and thus contributes to the efficiency of the cleaning process.

Abstract: A semiconductor device according to the invention of the present application includes a semiconductor chip having a plurality of electrodes provided on the surface thereof, at least one inner lead fixed to the surface of the semiconductor chip with an insulating layer interposed therebetween, a shielding plate placed in the neighborhood of a first side of the semiconductor chip, and a sealing resin for sealing the semiconductor chip, the inner lead and the shielding plate. The sealing resin is injected from the direction of a second side of the semiconductor chip, which is opposite to the first side of the semiconductor chip Therefore, the flow of the resin is controlled upon sealing so that the resin is uniformly injected.

Abstract: A first-in, first-out memory circuit includes first and second memory part respectively having first and second address locations each of which has a first word length, a write address counter outputting a write address signal and a memory part selection signal to the first and second memory parts in response to a word length selection signal, and a memory part enable circuit which is coupled between the write address counter and the first and second memory parts and receives the memory part selection signal. The memory circuit also includes a data bus which is applied with the input data and which includes a first data bus having the first word length and a second data bus having the first word length, and a data input part which is coupled between the data bus and the first and second memory parts.

Abstract: A method of manufacturing a cathode for a plasma etching apparatus includes steps for making the inside of holes formed in the cathode and the surface of the cathode a hard surface so as to prevent particle generation while the cathode is in use for etching a wafer. These steps include: a) forming a plurality of holes in a silicon substrate; b) carrying out a physical-surface treatment on the surface of the silicon substrate using slurry; and c) carrying out a chemical-surface treatment for removing protrusions inside the holes formed on the silicon substrate and on the surface of the silicon substrate using potassium hydroxide (KOH). The cathode manufactured by this method has a hard surface formed thereon and inside the holes, and the hard surface has no protrusions. Without protrusions, no particles can be generated from protrusions being etched and loosened during the etching process, so no particles adhere to the wafer being etched.

Abstract: A NOR-type mask ROM includes a semiconductor substrate of a first conductivity type. A plurality of buried diffusion regions of a second conductivity type opposite to the first conductivity type are arranged in parallel on the substrate to serve as sources and drains. A plurality of channel regions are defined between the buried diffusion regions and a plurality of gate insulating layers are formed on the channel regions. A plurality of gate regions are formed in parallel on the gate insulating layers, intersecting the buried diffusion regions, and overlapping with the channel regions, to be provided as word lines. An insulating layer is deposited on the overall surface of the substrate, covering the gate regions, and a plurality of sub-gate regions are formed into spacers on the sidewalls of the insulating layer, in parallel with the gate regions, for increasing a cell current.

Abstract: A valve cleaning apparatus and method provide for cleaning of heat resistant, scratch resistant coated valves using deionized water and at least one chemical mixture. The cleaning method includes sampling and analysis of the chemical mixture for the presence of metal impurities to within 0.5 to 1.5 ppb. Valves cleaned using this method and apparatus can then be transferred for use in semiconductor device fabrication equipment without the danger of metal impurities from the valves entering and damaging the fabrication equipment and the semiconductor devices being fabricated. The apparatus uses a single pumping device and a single return line, which are provided with selection devices to alternatively supply to or return from the valves either the deionized water or the chemical mixture. A plurality of same-sized or different-sized valves can be cleaned simultaneously.

Abstract: A wafer transfer method of semiconductor fabricating equipment is capable of successively arranging a plurality of wafers in a designated order (e.g., an ascending order, a descending order, an odd/even number order or an individual selection order). The wafer transfer method uses a first cassette containing the wafers, and a second cassette for receiving the wafers. A wafer transfer robot having a wafer transfer arm moves the wafers from the first cassette to the second cassette, after the wafer serial numbers have been read and sent to a computer. The computer uses a selected wafer arrangement order to decide where within the second cassette each wafer from the first cassette should be placed and then controls the wafer transfer robot to place each wafer into the desired location. With the wafers arranged in the selected order, it is not necessary to test each wafer after each fabricating process.

Abstract: A wafer transfer system of semiconductor fabricating equipment is capable of successively arranging a plurality of wafers in a designated order (e.g., an ascending order, a descending order, an odd/even number order or an individual selection order). The wafer transfer system includes a first cassette containing the wafers, and a second cassette for receiving the wafers. A wafer transfer robot having a wafer transfer arm moves the wafers from the first cassette to the second cassette, after the wafer serial numbers have been read and sent to a computer. The computer uses a selected wafer arrangement order to decide where within the second cassette each wafer from the first cassette should be placed and then controls the wafer transfer robot to place each wafer into the desired location. With the wafers arranged in the selected order, it is not necessary to test each wafer after each fabricating process.

Abstract: A programmable digital correlator device, and associated correlation method, with a very efficient structure. In one aspect, two or more correlators share a common data sequence shift register. In another aspect, the data sequence shift register is comprised of random access memory (RAM) modules which allow efficient construction in field programmable gate array (FPGA) logic devices. Two's-complement data samples are multiplied by a reference sequence to produce unfinished two's-complement products, the products are summed with unsigned arithmetic in an adder containing population counters, and a correction factor is added after all other calculations are complete to convert the unsigned result back to a two's-complement number.

Abstract: A non-volatile semiconductor memory apparatus having a memory matrix of inter-column arrangement type configuration divided into several segments performs a read operation based on a system that causes a current to flow into sense amplifiers from data lines. In this non-volatile semiconductor memory, memory cell transistors configured as memory cells are serially connected to form multiple memory rows. Word lines connect the gates of the transistors constituting the memory cells of each memory row. First column lines and second column lines connect the connection nodes between the memory cell transistors. The word lines and the first and second column lines constitute a memory array. Bit lines are connected to the second column lines, respectively. A bias electric potential supply line is connected to the first column lines via select transistors, respectively.

Abstract: An apparatus and method for on-line decomposition of a hydrogen peroxide solution, for use in fabricating a semiconductor device, includes a membrane tube having a porous plug inserted in each end, with the porous plugs defining a space where a platinum catalyst is disposed. A first coupling tube is inserted into one end of the membrane tube to supply a hydrogen peroxide sample to the membrane tube. The hydrogen peroxide contained in hydrogen peroxide sample is decomposed into water and oxygen gas according to an action of the platinum catalyst. A second coupling tube is inserted into a second end of the membrane tube to discharge a diluted hydrogen peroxide solution to an analytical instrument, where the decomposed hydrogen peroxide solution is analyzed on-line.

Abstract: A semiconductor device including a first area where a silicide layer is formed only on a gate electrode, and a second area where a silicide layer is formed both on the gate electrode and on source and drain areas is produced by a method wherein a polishing stopper and an oxide layer are sequentially stacked, the gate electrode is exposed in a self-aligned manner, and then a first silicide layer is formed to thereby suppress misalignment in the process of manufacturing a semiconductor device having a fine linear width. In the first area, when first and second insulating layers are stacked and contact holes are formed directly connected to the semiconductor substrate, a second silicide layer is formed at the bottoms of the contact holes, to reduce contact resistance and leakage current.