Abstract: A system includes a data structure having a Direct Table (DT), Patricia-Trees, Pointers and high speed storage systems such as Contents Address Memory (CAM). The DT has a plurality of entries with each one coupled to a Patricia Tree having multiple nodes coupled to leaves. The number of Nodes, termed a threshold, that can be traversed to obtain information in the leaves is limited to a predetermined value. Once the threshold is reached a pointer indicates the address of the CAM and the address of the leaves is stored in the CAM. By using the structure and method the latency associated with tree search is significantly reduced.

Abstract: A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer, and input signals from an array and a clock line providing current time. Also included is a decision block that determines which of the searches are critical and which, during peak calendar search periods, can be postponed with minimal impact to the system. The postponed searches are then conducted at a time when there is available calendar search capacity.

Abstract: Embodiments that design integrated circuits using a closed loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a viewer and a 1×N compiler. The viewer may generate displays of behavioral representations of 1×N building blocks, with the behavioral representations comprising RTL definitions. The 1×N compiler may create physical design representations of the 1×N building block and create behavioral representations from the physical design representations, wherein the physical design representations have elements altered by one or more tools of a tool suite.

Abstract: A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.

Abstract: A method and system for reducing an amount of horizontal space required when displaying a plurality of columns on a display screen is disclosed. The at least one column of the plurality of columns has at least one entry containing text data. The method and system include obtaining the at least one entry from the at least one column, and abbreviating a width of the at least one entry, determining if there is another entry containing text data. The method and system further include repeating the steps of obtaining the at least one entry, abbreviating the at least one entry and determining if there is another entry until all of the at least one entries are abbreviated. The method and system further include displaying the at least one column having the at least one abbreviated entry.

Abstract: A method for controlling the flows of data packets that are switched or routed at nodes of high-speed communication networks is disclosed. According to the invention, resource metering units are assigned to resources shared between devices of the switch or router e.g., shared memories or link bandwidths. When the occupancy of a shared resource reaches a predetermined threshold, an event is generated and transmitted to devices sharing this resource. Furthermore, a periodic refresh of the overall flow control information is performed so that lost events are, however, eventually acted on. Thus, a new device may become active without perturbing the active flows after having gathered enough flow control information.

Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.

Abstract: A method for dispatching instructions in the data processing system, having in memory for storing instructions and a plurality of central processing units, where each central processing unit includes a circuit to provide data indicating internal performance, the method having steps of receiving internal performance data signals from a pool of central processing units, selecting a central processing unit according to the received internal performance data and dispatching instructions from the memory to the selected central processing unit.

Abstract: A circuit for a multiplexer includes a pair of NAND gates with outputs coupled to an OAI gate constructed from a complementary circuit formed from solid state devices. A current flow controller formed from solid state devices is coupled to one of the NAND gates. When activated the controller inhibits the flow of current through the NAND gate and a portion of the OAI gate to which the controller is connected. As a consequence, leakage power is not consumed within the multiplexer. Several of the applications in which the circuit is used are also demonstrated in the specification.

Abstract: Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits include registers that are connected to a voltage regulation circuit that provides the integrated circuit voltage source and to a power management circuit. These measurement circuits provide signals to control the voltage regulation circuit for adjusting the voltage output to the integrated circuit based upon a measurement values obtained on the semiconductor device. These measurements include temperature, IR drop at locations on the semiconductor substrate, along with the frequency response of integrated circuit.

Abstract: A method and apparatus determines and sets operating voltage on a JTAG interface by incrementally increasing a test voltage applied thereto. The contents of a register is monitored to detect when the contents switch (change) from a first value to a second value. The voltage occurring at the switch is doubled to establish the operating voltage.

Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.

Abstract: An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.

Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.

Abstract: A signal detector and method to detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and reference paths are used for calibration which is done automatically by use of an embedded algorithm residing in a digital block. The calibration range and resolution are predetermined to cope with the technology, modeling, design methodology and human error.

Abstract: A generic method and apparatus for managing semaphores in a multi-threaded processing system has a storage area for each of the threads in the processing system. Each storage area includes a first part for storing at least one indicia for identifying at least one unique semaphore from a plurality of semaphores utilized by the multi-threaded processing system and a second part for storing an indicia for indicating a locked status for the stored semaphore. A thread requiring a semaphore sends a semaphore lock request to the semaphore manager which examines the contents of all of the storage areas to determine the status of the requested semaphore. If the requested semaphore is not locked, it is locked for the requesting thread by inserting the requested semaphore and locked status in the memory location assigned to the requesting thread.

Abstract: A method of forming a differential amplifier on a substrate which has a greater tolerance for applied voltages and a chip so formed. The differential amplifier circuit on a substrate has additional transistors connected with resistors which form a voltage divider, thereby sharing the voltage stress which may be applied and accommodating enhanced capabilities for the differential amplifier.

Abstract: A system for resequencing data packets is disclosed. In a preferred embodiment, the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter is further having a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location.

Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.

Abstract: Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first: match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.