Abstract: An on-chip clock generation system used the Serial Interface in an on-chip JTAG facility to write bit patterns in a shift register. The bit patterns are applied to control inputs of a clock generation circuit whose clock outputs are varied in accordance with changes to the bit patterns. By using the same facility to provide JTAG and clock functions the output clocks provided by clock generation circuit on the chip can be varied without using additional pins or the output clocks themselves.

Abstract: A method and system for automating the creation of test cases for logic designs. A comprehensive set of bus transactions characterizing a bus architecture is provided to a test case designer in a user interface. The designer may enter inputs corresponding to a particular design-under-test (DUT) via the interface. The interface processes the inputs to automatically generate a configuration file corresponding to the particular DUT. The configuration file may be processed by a generator program to automatically generate a test case comprising one or more bus transactions customized to the particular DUT.

Abstract: The present invention describes a system and method for independently verifying the Execution Rate of individual tasks by a device through simulation. Described is a situation in which a system has a main device through which data flows to and from other devices. Bus transfers must fall within required rates. A simulation of the configuration utilizes models of the various devices, including the “Main device”. This simulation is used to verify the data traffic and associated transfer rates. Data transfer includes random bursts, with randomly chosen periods between bursts. The data rate and data validity are measured during each burst period.

Abstract: A device that automatically configures the high speed (100 Mbps) port of a switch both physically and logically is provided. For physical configuration, the device determines the transmit pair conductor and the receive pair conductor interconnecting a switch port and Data Terminal Equipment (DTE). The switch port can be termed “Primary” while the connected DTE is termed “Secondary” or vice versa. For logical configurations, the device makes the determination. The device includes a switching relay, a controller and impedance matching transformers. The controller switches the connections between the relay and the transformer so that the impedance is substantially constant even though the output from the high speed port is feeding different resistive transmission lines.

Abstract: To insure connection resiliency two LECs are defined in normal practice in which a lengthy and extensive recovery procedure is enforced in case of an ATM interface failure. In the present invention only one LEC is configured. This LEC is configured to be If the active ATM interface fails, the bridge is not notified of the failure as would normally happen. The LEC associates itself with the alternate ATM and rejoins the ELAN via the alternate ATM interface. The ELAN Join Procedure is one of the LAN Emulation protocols. After the ELAN has rejoined, the LEC automatically re-establishes the previously existing Data Direct VCCs (bi-directional point to point LAN Emulation connection established from one LEC to another) using its LE_ARP (LAN Emulation Address Resolution Protocol) cache entries.

Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to service based on minimum bandwidth specifications where position in the queue is adjusted after each service based on minimum bandwidth specificaiton and the length of frame, a process which is subject to rounding errors. To avoid the accumulation of rounding errors inequitably influencing the position of some in the queue, a system to adjust for the rounding errors adds an increased measure of fairness to the system.

Abstract: A system and method uses grouped calendars, flow queues, pointers and stored rules to process information packets so that different flow control characteristics associated with the information units are maintained.

Abstract: Methods systems and computer program products are provided for hashing address values that exhibit banding in a plurality of regions of an address space defined by at least two segments of the address values, by performing at least one of a translation and a rotation of the at least two segments to thereby map the at least two segments from the plurality of regions to one of the plurality of regions.

Abstract: A method, system, program product, and data structure for processing network communication within a communication network from a general processor to a network processor. An informational frame is encapsulated into a packet for transmission within a communication network from a general processor to a network processor having a data processor and a control processor. If the informational frame is a control frame and the control processor is congested and if the control frame only needs message routing services from the locally connected network processor, the encapsulated packet is designated as a data-type packet so that the data processor processes the control frame. The encapsulated packet is then sent from the general processor to the network processor. The data processor decapsulates the encapsulated packet, parses the control frame and processes the control frame.

Abstract: A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex with a suite of peripherals, all formed on a common semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.

Abstract: A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors formed on a semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.

Abstract: A system and method for requesting, providing, and displaying data relating to performance of a network is disclosed. In one aspect, the method and system include allowing a user to select the at least one system from which data is requested, identify at least one data type for which data is requested, select a sampling interval for sampling data for the at least one data type, and identify a time period for which data of the at least one data type is requested. In an second aspect, the method and system include receiving the request, retrieving at least one value for the at least one data type if the at least one data type is available on the at least one system, and calculating an average value for the sampling interval. The method and system include saving the average value for the sampling interval in a report and repeating the retrieving, calculating, and saving steps for each sampling interval in the time period.

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

Abstract: A method and system are disclosed for allocating data input bandwidth from a source link to a plurality of N data queues each having a variable occupancy value, Qi(t), and a constant decrement rate, Di, where i designated the ith queue among the N queues. First, a threshold occupancy value, T, is designated for the N queues. During each time step of a repeating time interval, &Dgr;t, the occupancy value, Qi, is compared with T. In response to each and every of said N data queues having occupancy values exceeding T, pausing data transmission from the source link to the N data queues, such that overflow within the data queues is minimized. In response to at least one of the N data queues having an occupancy value less than or equal to T, selecting one among the N data queues to be incremented, and incrementing the selected data queue, such that underflow of the selected queue is minimized. In the context of scheduling one cell per time step, the value of T is one.

Abstract: A method and structure for managing computer hardware cable media is provided, featuring a support having a frontal face, at least one flange, and at least one curved surface projecting from the support frontal face for receiving and guiding cable media. The curved surface has a radius sufficiently large enough to receive and redirect cable media by bending the cable media without cracking or causing other damage to the cable media. The flange is connected to a computer rack system rail so that support is overlapping at least one hardware component connected to the computer rack system, thereby allowing a portion of the rack space occupied by the flange and the support to be utilized by other hardware components, increasing the effective usable space of the rack system. Cable media are received onto the curved surface, redirected by bending along the curved surface, and ultimately distributed in discrete bundles of cable media to hardware devices.

Abstract: A system that generates data waveforms for transmission on a communications network includes a series of sequentially over sampled and switch current sources whose timings are locked to a master delay line and replicas thereof. The master delay is configured as a ring oscillator with its frequency looked to a precise clock reference. The clock controls the rise and fall of the data waveforms thus making them immune to variations in semiconductor processes used to implement the system.

Abstract: In an electronic system such as a communications integrated circuit including a plurality of components, e.g., transmitters, each of which are operative to demand current responsive to a control signal applied thereto, an apparatus for time-distributing current demand comprises a first phase control circuit configured to receive a reference clock signal and operative to generate a synchronized output signal therefrom, the first phase control circuit generating a phase control signal for synchronizing the output signal to the reference clock signal. A plurality of second phase control circuits is responsive to at least one input control signal and to the phase control signal and operative to apply a plurality of phased output control signals to the plurality of components, the phased output control signals phased with respect to one another by time intervals that are dependent upon the phase control signal.

Abstract: Method and apparatus for segmenting variable length frames into fixed length cells in a network equipment. The method allows preparing information to build the cells resulting in the segmenting of a succession of frames directed to the same destination in said network equipment. The cell may be packed with more than one frame. The cell information comprises the address where to read the frame data in a first storage unit, the cell header itself which indicates if the cell includes data from one packet or for more packets, a pointer per each of said more packets, designating the place of the end of data of the previous packet in the cell and a cell type field indicating one of the following types: a start of a new frame type, a continuation of frame type, a end of current frame type and a start and a end of a new frame type. The segmenting apparatus comprises a finite state machine using an Add/substract unit to compute the cell information and write said cell information in a second storage unit.

Abstract: A microprocessor based system, such as a Personal Computer (PC), server, router, word processor or like devices, includes circuit arrangement that monitors the processor for a heartbeat pulse. If the heartbeat pulse is not sensed within a specified time interval the circuit arrangement issues a Soft Reset signal (Unmasked Interrupt) that causes the microprocessor to execute a program that logs the current state of selected entities within the system and a Hard Reset Pulse that resets the system hardware. The log can be used to identify the cause of a problem, whereas the Hard Reset causes the system to reboot and continue normal operation.

Abstract: Auto-adaptive method of load balancing in a data transmission system wherein one active station (32) amongst a plurality of stations requests the access to the resources of a host (10), the active station being connected to a connected-oriented network linked to host (10) by means of a plurality of communication controllers (12, 14, 16) identified by the station (32) with the address of host (10), the connected-oriented network implementing a protocol in which route discovery frames are sent from the station (32) to all the communication controllers (12, 14, 16) and response frames are sent back with a predefined delay from each one of the communication controllers to the station (32), whereby the station (32) selects the route defined by the first received response frame, this method being characterized in that the delay to apply to the response frame is at each moment dynamically defined by using a logarithmic function of the current number of active stations.