Abstract: An apparatus and method that correct skew associated with data receive from different transmission links. A known training pattern is sent through the transmission links. The training pattern is recovered and forwarded through delay registers/selecter logic to a memory buffer. A programmed controller accesses the memory and searches for the training pattern. If the training pattern is found for each transmission link, the offsets between the transmission links are determined and are used by the delay registers/selecter logic to adjust the position of the pattern so that the patterns from each link is linearly aligned within the memory buffer.

Abstract: A shared digital subscriber line modem achieves reduced total power consumption and data security by generating and transmitting a physical data frame which includes a control channel and a data field to only the connected client modem associated with the intended recipient. A second physical frame which does not include the data field is generated and transmitted to all of the other connected client modems. This method results in a reduction in the power required and provides improved data security by preventing data access to non-addressed client modems.

Abstract: A method for automatically generating a network subnet configuration, monitors IP Address Resolution Protocol (ARP) frames on the network and builds and maintains a table which includes a list of learned subnets, the ports or forwarding domain associated with each of the learned subnets and a mask associated with each learned subnet for identifying hosts belonging to the subnet. The from and to IP addresses from intercepted IP ARP frames are examined to determine if the IP addresses belong in any of the learned subnets. If neither IP address belongs to an existing learned subnet a new learned subnet is established. The subnet includes the common prefix bits of both IP addresses, a mask identifying those bits and the port over which the ARP frame was received. If only one IP address belong to a learned subnet, the mask associated with that subnet is modified to include the common prefix bits of both IP addresses and the forwarding domain is adjusted.

Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a weighted fair queueing system where the position of the next service in a best efforts system for using bandwidth which is not used by committed bandwidth is determined based on the length of the frame and the weight of the particular flow.

Abstract: The present invention discloses method for packaging and assembly of electronic units comprising a multi-planar board system in which each single planar board provides electrical contacts and/or signal drive to its successive planar board via a flexible cable forming the only connection between successive planar boards. In its packaged position the planar boards are laid upon one another without affixing them with each other or affixing them with the housing of the electronic unit, wherein the packaging of the planar boards preferably forming a daisy chain. Positioning and adjusting of the planar boards to each other is mainly achieved by the cover element being wrapped around all surfaces of the planar boards during the packaging process, positioning and clamping of the packaging of the planar boards within the housing is mainly achieved by the self-adapting suspension during the assembly process of the electronic unit into the housing.

Abstract: Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.

Abstract: Stations in a communications network are awakened by matching a pattern received from the communications network with patterns in the stations. When a match occurs, the stations are awakened. The patterns are arranged contiguously on word boundaries. A nibble (4 bits) in a mask word identifies the part of the pattern word to be used in the comparison.

Abstract: A mechanism controls a multi-thread processor so that when a fist thread encounters a latency event to a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.

Abstract: The present invention provides a notebook PC with a monitor that enables a user to have better handling of the PC and viewing of the display of the device when using the PC. A PC includes a monitor and a main unit that are connected to each other by an arm through a first hinge portion and a second hinge portion. In the present invention, the angle of tilting of the monitor is constantly maintained even when the position in height of the monitor is changed.

Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.

Abstract: The transport protocol for communicating between general purpose processors acting as contact points and network processors in a packet processing environment such as Ethernet is provided. In such an environment, there is at least one single control point processor (CP) and a plurality of network processors (NP), sometimes referred to as blades. A typical system could contain two to sixteen network processors, and each network processor connects to a plurality of devices which communicate with each other over a network transport, such as Ethernet. The CP typically controls the functionality and the functioning of the network processors to function in a way that connects one end user with another, whether or not the end user is on the same network processor or a different network processor.

Abstract: This system represents a customizable simulation model of an ATM/SONET Framer for System Level Verification and Performance-Characterization. An Asynchronous Transfer Mode (ATM) data processing ASIC interfaces with a Media Access Control (MAC) device that presents an electrical data path interface, called Universal Test & Operations PHY Interface for ATM (UTOPIA), using ATM protocol on the ASIC side and simplex optical interfaces using Synchronous Optical Network (SONET) protocol on the network side. Such a MAC device, commonly referred to as ATM/SONET Framer, provides one Receive and one Transmit interface to the network at various SONET line rates such as 155.52 Mbps (OC-3), 622.08 Mbps (OC-12), 2488.32 Mbps (OC-48), etc. The ATM and the SONET interfaces operate on different clock frequencies and thus represent two distinct clocking domains. The data interchange between the two clocking domains is achieved via FIFO buffer elements and associated control and status signals.

Abstract: A power supply system and a power supply control method capable of having a peak shift function without deteriorating the essential function of an apparatus is provided for such that the present invention provides for the use of the peak shift function without deteriorating the essential function of an electrical apparatus.

Abstract: The decision to discard or forward a packet is made by a flow control mechanism, upstream from the forwarding engine in the node of a communication network. The forwarding engine includes a switch with mechanism to detect congestion in the switch and return a binary signal B indicating congestion or no congestion. The flow control mechanism uses B and other network related information to generate a probability transmission table against which received packets are tested to determine proactively whether a packet is to be discarded or forwarded.

Abstract: A network apparatus comprising storage units storing configuration information about the network apparatus, an input network interface to at least one network physical line, at least one processor receiving network data from said network interface, processing said data, storing information about said network data in said storage units, storing said data as formatted data units in said storage units, a first bus interface to two bus connections, a first hardware component reading said configuration information and said information about data stored in said storing units and steering said formatted data units stored in said storage units to at least one of the two bus connections of said first bus interface, a second bus interface to two bus connections, an output network interface to at least one network physical line, a second hardware component reading formatted data units arriving on at least one of the two bus connections of said second bus interface and storing said formatted data units in said storage un

Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.

Abstract: A cooling apparatus, method and article of manufacture are disclosed which provide for selectively providing power to an attached heat-dissipating apparatus having a cooling probe in thermal contact with a cooling unit, to remove heat generated by a heat-generating source within the computer to an external environment outside of the computer. Power may be conserved, portable battery life extended, higher-speed processors utilized, and overall dimensional characteristics of a personal computer may be slimmed and reduced by utilizing the apparatus with a personal computer. Heat energy is transferred across a thermal connection interface from the heat-generating source of the personal computer to a collection face of the apparatus, and thereafter collected heat energy is dissipated in relation to the available power of the power source and/or the planned operating speed of the processor.

Abstract: A symmetrical preform that provides protection to an equipment component (or other fragile or breakable item), provides ease in use during pre-packing and packing of an equipment component for transport, does not require the need for additional packing components in combination with the packaging assembly, and is economically suited for its end use, is provided for. Accordingly, the present invention provides a method for making an integral, one piece packing assembly having symmetrical characteristics and being comprised of a flexible, corrugated-shaped material that is capable of protectively encapsulating, in a predetermined arrangement, a fragile component to ready for further movement, transport or packaging.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

Abstract: A method of calculating capacity of an intelligent battery is provided for, whereby an intelligent battery and a portable electronic device are capable of allowing for power consumption by a minute current undetectable by a conventional circuit without any special cost required so as to consequently allow an error of capacity data to be smaller.