Abstract: A network device including an ingress processor and egress processor which receives frames of data over the network on an input port, and transfers it to an appropriate output port. The received frame is processed by an ingress processor which prepares an intra-switch frame for delivery to an egress processor serving a relevant output port of the switch. The intra-switch frame includes a frame header having parameters which have been determined by the ingress processor, as well as data indicating an address for the egress processor for beginning processing of the frame. By identifying to the egress processor processing which has already taken place, the egress processor is relieved of any redundant processing of the frame. The egress processor provides a hardware frame classifier which decodes the information contained in the intra-frame header to derive parameters which have been previously computed as well as a starting address for the egress processor.

Abstract: A network processor is used for the routing of objects in non-data networking applications. The processor utilizes the Open Shortest Path First (OSPF) algorithm to capitalize on the benefits of data control for object traffic control and costs. A network processor is used at each point in a grid represented by intersecting paths. One or more routing tables are embedded in each network processor. Each routing table describes links with other network processors in the grid to which the network processor is interconnected. A cost factor is associated with each link and is constantly updated by the OSPF as new information becomes available. If a link or route becomes unavailable, the cost is set at infinity. The system then creates an alternative path for the object between a source and the desired destination that bypasses the unavailable link or route.

Abstract: A control mechanism is established between a network processor and a tree search coprocessor to deal with latencies in accessing the data such as information formatted in a tree structure. A plurality of independent instruction execution threads are queued to enable them to have rapid access to the shared memory. If execution of a thread becomes stalled due to a latency event, full control is granted to the next thread in the queue. The grant of control is temporary when a short latency event occurs or full when a long latency event occurs. Control is returned to the original thread when a short latency event is completed. Each execution thread utilizes an instruction prefetch buffer that collects instructions for idle execution threads when the instruction bandwidth is not fully utilized by an active execution thread. The thread execution control is governed by the collective functioning of a FIFO, an arbiter and a thread control state machine.

Abstract: An ordered semaphore management subsystem and method for use in an application system which includes a plurality of processors competing for shared resources each of which is controlled by a unique semaphore. The subsystem generates an ordered semaphore field (OSF) corresponding to each processor in a linked list of processors and assigns one of four statuses to the OSF depending on the position the processor occupies in the linked list of processors competing for the shared resources. The four states are (1) semaphore head (SH); (2) behind semaphore head (BSH); (3) semaphore head behind (SHB); and (4) skip (Skip). Only the SH processor is allocated the semaphore when requested. A processor not in the SH state will be denied the semaphore even if is available to assure sequential access.

Abstract: A stateless message-passing scheme for interactions between a network processor and a coprocessor is provided. The network processor, when receiving data frames for transmission from a network element to another network element encapsulates the entire packet that it receives within a frame. In this frame, there is provided a header field and a data field. The data field contains the data that needs to be transferred, and the header field contains all of the information regarding the deep-processing that the coprocessor is to perform so that no information of any type need be stored either by the network processor or separately regarding the processing of the data in the data packet. The coprocessor performs the operation designated by the header and returns the altered packet and header to the network processor.

Abstract: An interface to interconnect chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The chips can be configured in different operational modes which dictates what portion of a frame is to be transmitted between selected chips of the system.

Abstract: A global architecture for a serial link connection between two cards which must transmit data across wired media is provided. The architecture comprises a transmitter portion and a receiver portion. The transmitter portion includes a structure and circuitry to take digital bits from a first bit register, such as for example, an eight-bit register or a ten-bit register, and convert these bits into serial analog transmission to the receiver portion. The receiver portion includes a structure and circuitry to sample the analog transmission of the original digital bits and reconvert the analog serial signal of the digital bits corresponding to the original digital bits and store them in a second bit register comparable to the data stored in the original register from which they were selected.

Abstract: This invention reduces power consumed during CAM search operations in a CAM/RAM structure utilizing a segmented match line structure. This device is useful when it is known that a portion or portions of the compare data inputs vary infrequently. The apparatus sometimes may be referred to as local match line hold latch, and is a device that stores the value of a local match line comparison result the first time that a search operation occurs, and will stay at that value until the value of the compare data in of the local match line changes.

Abstract: A packet network redistributes excess bandwidth for voice and data sessions applying a Quality of Service (QoS) algorithm. The network includes interacting client stations using H.323 protocol managing bit rate according to an algorithm as voice and data sessions are added or removed from the network. The client stations include codecs coupled to the network. The codecs provide voice sessions at a minimum bandwidth using a voice codec bit rate and preferred bandwidth using another voice codec bit rate. A first algorithm applies the QoS algorithm allocating bandwidth between interacting client stations after the addition of a new voice or data session when there is insufficient bandwidth for the new session to receive preferred bandwidth. A second algorithm is applied when a voice or data session is removed from the interacting client stations. If any session is allocated minimum bandwidth the QoS increases a voice session at minimum bandwidth to preferred bandwidth if excess bandwidth is available.

Abstract: A codec detects congestion in a packet network and responds via a session control protocol to re-negotiate codec-type and/or parameters with the receiving codec to reduce bit rate for supporting a session. Once the connection and session are established, encoded packets start flowing between the two codecs. A control entity sends and receives network congestion control packets periodically in the session. The congestion control packets provide a “heartbeat” signal to the receiving codec. When the network is not congested, all “heartbeat” packets will be passed through the network As network congestion increases, routers within the network discard excess packets to prevent network failure. The codecs respond to the missing packets by slowing down the bit rate or proceeding to renegotiate a lower bit rate via the session control protocol. If there are no missing packets, the codecs detect if the session is operating at the highest bit rate, and if not, re-negotiate a higher bit rate.

Abstract: Method and system of transmitting a loopback cell of a connection established between a source ATM device and a destination ATM device of an ATM network, with the loopback cell being returned to one of the switching nodes located on the route used by the connection, and entering the switching node by a port of an adapter and going out of the switching node by the same port of the same adapter instead of another connected adapter used by normal cells of the connection.

Abstract: A data switch is provided which routes fixed-size data packets from input ports to output ports, using shared memory which holds a copy of each packet in buffers. Output ports have a queue which contains pointers to buffers holding packets bound for that port. The number of shared memory buffers holding packets is compared to the number of buffer pointers in the output queues. In this way, a Multicast Index (MCI), a metric of the level of multicast traffic, is derived. The switch includes a Switch Core Adaptation Layer (SCAL) which has a multicast input queue. Because traffic is handled based on priority class P, a multicast threshold MCT(P), associated with the multicast input queue, is established per priority. While receiving traffic, the MCI is updated and, for each priority class in each SCAL, the MCI is compared to the MCT(P) to determine whether corresponding multicast traffic must be held.

Abstract: A packet network congestion control system using a biased packet discard policy includes a plurality of end points having codecs operating in a framework, e.g. ITU-T H.323 protocol to establish a communication session. The protocol enables the codecs to negotiate codec type and associated parameters. Once a connection and session are established, compressed voice and data packets start flowing between the two end points. A control entity supplies congestion control packets periodically. The control packets provide a “heartbeat” signal to the codec at the other end of the session. Each codec receiver uses the “heartbeat” signal as an indication of network congestion. As network congestion increases, routers within the network discard excess packets to prevent network failure. The network discards all packets classified as congestion control packets whenever a flow control mechanism detects congestion or a trend toward congestion.

Abstract: Apparatus, program product and method that schedules movement of packets within network devices, such as network processors, includes a time based calendar in which a segmented hierarchical routine is used to identify the calendar location of the next flow queue from which a packet is to be forwarded.

Abstract: Data bandwidth on a congested link of a Carrier Sense Multiple Access with Collision Detection (CSMA/CD) network, is controlled by a Pause MAC Frame which carries information identifying devices causing the problem on the link. The Recipient of the Pause MAC Frame can use the information to deactivate selected devices on the congested link. As a consequence, the data bandwidth is reduced without shutting down the link.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

Abstract: A method and system for transmitting a loopback cell within an ATM connection. The method comprises the steps of detecting in an input adapter whether or not an incoming ATM cell includes a loopback condition indicator. If so, specific routing labels are appended to the incoming ATM cell indicating that the incoming cell is a loopback cell to be looped back on the connection such that the switch engine of the switching node transfers the loopback cell to the same port of the input adapter utilizing the appended routing labels.

Abstract: In a network node, a method and apparatus to assemble fixed cell length cells resulting from the segmenting of variable length frames into cells. The hardware implementations of the preferred embodiments of the invention comprise a finite state machine which handles three processes at the same time, one for fetching the frame data stored in a storage unit, the data store, one for moving data from the frame data and control block data to the cell and one for outputting cell data. The other components are a counter for the pointing to the frame and a multiplexer for selecting the correct data to form the cell.

Abstract: A system and method of reducing the input and output pins used to interface a fast serial port Ethernet processing system using multiplexing. Using the system of the present invention, four pins can allow a plurality of Ethernet communication paths to be connected to a single processor on a substrate. These four connections include a clocking input as well as a strobe signal which coordinates the multiplexing and identifies the time period for a predetermined source. The physical layer and the processor are each provided with a multiplexor which is controlled by the strobe to select the network to be coupled at any given time. The multiplexor includes a counter which is incremented by the clocking input and reset by the strobe signal.

Abstract: A low power DSL modem transmitter, suitable for incorporation in integrated DSLAM server line cards, transmits full power physical frames which include a control channel and a data field when data is available for transmission and physical frames having only a control channel or a control channel and a low power synchronization field when data is not available for transmission. And a method for controlling the total power dissipated in the integrated DSLAM by selectively restricting the flow of data packets to the DSLs.