Abstract: A method used to form a semiconductor device comprises providing first and second circuit portions having first and second pad portions respectively. The second circuit portion is electrically isolated from the first circuit portion. The first and second pad portions are then electrically connected, for example with a ball bond or a wire bond, to electrically couple the first and second circuit portions. In various embodiments the semiconductor device will not function until the pad portions are electrically coupled, and in other embodiments the functionality of the device may be selectively controlled by connecting selected pad portions from a plurality of pad portions. Isolating the first and second circuit portions allows electrical operations such as antifuse programming to be carried out without adversely affecting related circuits. Once electrical operations are completed, the isolated circuit portions are electrically coupled to provide a complete circuit.

Abstract: A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along each gate, a plurality of conductive plugs each contacting the wafer, and a BPSG layer overlying the transistor gates and contacting the active area. A portion of the BPSG layer is etched thereby exposing the TEOS caps. A portion of the BPSG layer remains on the active area after completion of the etch. Subsequently, a portion of the TEOS caps are removed to expose the transistor gates and a titanium silicide layer is formed simultaneously to contact the transistor gates and the plugs. An inventive structure resulting from the inventive process is also described.

Abstract: A method for forming an electrical contact for a semiconductor device comprises the steps of providing a semiconductor wafer section having a major surface with a plurality of conductive pads thereon and electrically coupling each pad with an elongated electrical interconnect. Next, each electrical interconnect is encased in a dielectric and the dielectric is sectioned to expose a portion of each interconnect. An inventive structure which can be formed by the inventive method is also described.

Abstract: A method used to manufacture a semiconductor device comprises providing a first conductive container capacitor top plate layer and etching the first conductive container capacitor top plate layer to form a plurality of openings therein. Subsequently, a container capacitor bottom plate layer is formed within the plurality of openings in the top plate layer such that the bottom plate layer defines a plurality of openings. A second conductive container capacitor top plate layer is formed within the plurality of openings in the bottom plate layer. The first conductive container capacitor top plate layer is electrically coupled with the second conductive container capacitor top plate layer. The first and second conductive container capacitor top plate layers and the container capacitor bottom plate layer form a plurality of container capacitors. A structure resulting from the method is also disclosed.

Abstract: A method used to form a semiconductor device comprises forming a polysilicon layer, forming a conductive barrier layer on the polysilicon layer, then forming a conductive nitride layer on the conductive barrier layer. Next, a conductive amorphous layer is formed on the conductive barrier layer, and an elemental metal layer is formed on the conductive amorphous layer. Without the conductive amorphous layer the elemental metal layer would form on the conductive nitride layer as a small grained, high resistance layer, while it forms on the conductive amorphous layer as a large grained, low resistance layer. A semiconductor device which may be formed using this method is also described.

Abstract: A hard mask comprising boron-doped amorphous carbon, and a method for forming the hard mask, provides improved resistance to etches of a variety of materials compared with previous amorphous carbon hard mask layers.

Abstract: An antireflective layer formed from boron-doped amorphous carbon can be removed using a process which is less likely to over etch a dielectric layer than conventional technology. This layer can be removed by exposing the layer to an oxygen plasma (i.e. an “ashing” process), preferably concurrently with the ashing and removal of an overlying photoresist layer. An inventive process which uses the inventive antireflective layer is also described.

Abstract: A method and apparatus for removing layers from a circuit side of a semiconductor die includes the use of a holder, for example a semiconductor wafer having an opening therein for receiving the semiconductor die. Additionally the holder can include one or more layers thereover which are removed at a similar rate as those layers which comprise the semiconductor die. A die is placed into the opening and a circuit side of the die is aligned with a front side of the holder, for example using a generally planar surface, and is secured to the holder with an adhesive material. Using a holder reduces uneven layer removal which is known to occur in conventional processing, for example excessive removal at the edges of the die. A potting jig which aids in aligning and securing the die to the holder is also described.

Abstract: A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectric is formed over these conductive structures, then a portion of the first dielectric layer is removed which forms a hole in the dielectric layer to expose the second conductive structure. Subsequently, the second conductive structure is removed to leave a void or tunnel in the dielectric layer where the second conductive structure had previously existed. Finally, a second dielectric layer is provided to fill the hole but to leave the void or tunnel in the dielectric layer subsequent to the formation of the second dielectric layer. An inventive structure resulting from the inventive method is also described.

Abstract: A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly-selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.

Abstract: A memory module for an electronic device provides means for reducing the amount of power necessary to access a desired number of data bits. This provides a design of memory modules which requires fewer DRAMs to be turned on during a read or write cycle than present module designs, thereby using much less power.

Abstract: A method used during the formation of a semiconductor device reduces ion channeling during implantation of the wafer. The method comprises providing a semiconductor wafer and an unetched transistor gate stack assembly over the wafer. The unetched transistor gate stack assembly comprises a gate oxide layer, a control gate layer, a metal layer, and a dielectric capping layer. A patterned photoresist layer is formed over the unetched transistor gate stack assembly, then each of the capping layer, the metal layer, the control gate layer, and the gate oxide layer is etched to form a plurality of laterally-spaced transistor gate stacks. A screening layer is formed overlying the semiconductor wafer between the transistor gate stacks. A dopant is implanted into the semiconductor wafer through the screening layer, then the screening layer is removed.

Abstract: A method used to manufacture a semiconductor device comprises providing a first conductive container capacitor top plate layer and etching the first conductive container capacitor top plate layer to form a plurality of openings therein. Subsequently, a container capacitor bottom plate layer is formed within the plurality of openings in the top plate layer such that the bottom plate layer defines a plurality of openings. A second conductive container capacitor top plate layer is formed within the plurality of openings in the bottom plate layer. The first conductive container capacitor top plate layer is electrically coupled with the second conductive container capacitor top plate layer. The first and second conductive container capacitor top plate layers and the container capacitor bottom plate layer form a plurality of container capacitors. A structure resulting from the method is also disclosed.

Abstract: A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely-spaced regions, such as a memory transistor array, and widely-spaced regions, such as a periphery. Under conditions specified, the dielectric layer forms to have a first thickness over the closely-spaced regions and a second thickness over the widely-spaced regions. The second thickness is much thinner than the first thickness and dielectric over the widely-spaced regions may be etched away with a blanket etch which leaves the majority of the dielectric layer over the closely-spaced regions.

Abstract: A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

Abstract: A method for forming a ruthenium metal layer on a dielectric layer comprises forming a silicon dioxide layer, then treating the silicon dioxide with a silicon-containing gas, for example silicon hydrides such as silane, disilane, or methylated silanes. Subsequently, a ruthenium metal layer is formed on the treated dielectric layer. Treating the dielectric layer with a silicon-containing gas enhances adhesion between the dielectric and the ruthenium without requiring the addition of a separate adhesion layer between the dielectric layer and the ruthenium metal layer.

Abstract: A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the dielectric during the etch. The charge buildup along a top and a bottom of the sidewall can reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer is formed which electrically shorts the upper and lower portions of the sidewall and eliminates the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and in-process structures are described.

Abstract: A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features therein in spaced relation to each other which define an opening therebetween. A blanket polysilicon is formed over the wafer assembly and within the opening. A patterned photoresist layer is formed over the polysilicon layer, then the polysilicon layer within the opening is etched with a first etch. Subsequent to said first etch, the polysilicon with the opening is etched with a second etch comprising a halogen-containing gas flow rate of from about 35 sccm to about 65 sccm and an oxygen-containing gas (for example HeO2) flow rate of from about 12 sccm to about 15.6 sccm.

Abstract: A method for etching silicon nitride selective to silicon dioxide and silicon (polycrystalline silicon or monocrystalline silicon) comprises the use of oxygen along with an additional etchant of either CHF3 or CH2F2. Flow rates, power, and pressure settings are specified.

Abstract: A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.