Abstract: A "leads over chip" lead frame design is disclosed which can be used with a conventional die having leads located at the periphery. The inventive design uses an elongated tie bar which extends from one side of the lead frame to the other, across the die. The die is attached to the bottom of the tie bar, then the bond pads are wire bonded to the lead fingers. The lead fingers of the inventive lead frame do not extend over the top of the die, but are positioned in close proximity to allow for short bond wires. The die and a portion of the lead fingers are encapsulated, and the tie bars are severed to separate them from the lead frame. The invention allows the advantages of a leads over die configuration with a conventional die having bond pads located at the periphery. Therefor, a single die can be manufactured which can be used either with the inventive lead frame for a plastic package, or with a ceramic package.

Abstract: A method and apparatus for calibrating and performing statistical capability analysis of a pick-and-place machine comprise loading a glass fiducial plate onto a workholder of a pick-and-place machine, loading a glass slide onto a part placement nozzle of the pick-and-place machine, and placing the glass slide onto the plate. Alignment of a chrome fiducial on the fiducial plate with a chrome target window on the slide is examined. Responsive to the alignment of the target and the fiducial, key calibration codes in calibration software of the pick-and-place machine are adjusted. Once calibration is complete, multiple placement cycles using the glass fiducial plate and glass slides are performed to determine the statistical placement capability of the pick-and-plate equipment.

Abstract: A flash programmable memory device comprises first and second row lines each having memory elements therealong with the second conductive line functionally replacing the first conductive line. The memory device further includes a first program circuit for programming the memory elements along the first row line, and a second program circuit for programming memory elements along the second row line. A read circuit bypasses the first conductive line during all read cycles and reads the memory elements along the second row line.

Abstract: An apparatus for testing an unencapsulated, diced semiconductor device comprises a test head. The test head comprises a carousel table having a chamfered portion and a chamfered pedestal. While testing is pending the pedestal rests against the chamfered portion of the carousel table, and the pedestal receives a semiconductor device to be tested. The carousel table rotates 90.degree. to position the semiconductor device under the test head. The pedestal is lifted, and the chamfered nature of the pedestal and the carousel table allow for adjustments to the pedestal in the X-, Y-, and theta-directions to align the die with a probe responsive to signals from a camera positioned above the probe. Once the die is aligned, the pedestal continues to rise until contact is made between bond pads on the die and the probe, and testing is performed.

Abstract: A programming method for flash erasable programmable memory devices (flash EPROMs) comprises a first step of erasing the array of cells, then applying a control gate voltage to access a number of control gates. Any number of control gates can be accessed, but accessing four or eight control gates may have advantages. Regardless of the number of control gates accessed, a digit line voltage is applied to access one of the digit lines, which activates a number of cells. The digit line voltage is sensed for a voltage drop, which indicates the presence of at least one over-erased activated cell. If a digit line voltage drop is detected, a sense voltage is applied to each of the activated cells to determine which is over-erased. A heal voltage is applied to the over-erased cell for an interval of time to store electrons on the floating gate of the over-erased cell.

Abstract: A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

Abstract: An integrated circuit (IC) device comprises towers of bonded gold balls located on each bond pad. The towers allow for early encapsulation of the IC die. The IC can then be tested and attached to tab tape or a printed circuit board without particulate contamination concerns.

Abstract: A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and the field oxide region to form a trench. The trench comprises a bottom and a first sidewall consisting of silicon and a second sidewall comprising field oxide. The etching step removes a part of a doped region in the substrate. Next, a blanket nitride layer and a blanket oxide layer is formed over the substrate, and a spacer etch is performed on the nitride and oxide layer leaving nitride and oxide over the first and second sidewalls. The trench bottom is oxidized to form a layer of oxide over the bottom of the trench thereby insulating the trench bottom, and the oxide encroaches under the nitride and oxide on the sidewalls to join with the field oxide.

Abstract: A process useful for isolating active areas of semiconductor devices in which an isolation trench is created in a substrate, the isolation trench being lined with an oxidation barrier and filled with a thick film. An oxidation step is performed in which the thick film is oxidized. The oxidation is self-limiting as the oxidation barrier prevents the substrate surrounding the trench from being oxidized.

Abstract: A method of forming contact to a semiconductor memory device feature comprises the steps of forming a first oxide layer over a feature such as a semiconductor substrate or a conductive line or plate, then forming a hard mask over the first oxide layer. A first patterned resist layer is formed on the hard mask, then the hard mask is patterned using the first resist layer as a pattern. The first resist layer is removed and a second oxide layer is formed over the hard mask. A second patterned resist layer is formed over the second oxide layer and the second oxide layer is etched using the second resist layer as a pattern while, during a single etch step, the first oxide layer is etched using the hard mask as a pattern, the hard mask functioning as an etch stop.

Abstract: A method and structure for a programmable read-only memory comprises a thin gate oxide over a source region and a thick gate oxide over the drain region. A semiconductor substrate is lightly doped and has regions of thin sacrificial oxide overlying what will become the transistor channel, source, and drain, and thick field oxide. The region that will become the transistor source is protected with photoresist, and the drain region and a portion of the channel is doped, for example, with boron. The resist and sacrificial oxide is stripped, and gate oxide is formed from the exposed silicon substrate. The more heavily doped drain and channel regions oxidize at a faster rate than the lightly doped source region, and thus the gate oxide formed is thicker. Floating and control gates are formed over the channel region, covering both the thicker and thinner gate oxide.

Abstract: A process for forming field oxide on a semiconductor substrate having reduced field oxide thinning comprises forming an oxide layer over a semiconductor substrate, and forming a protective layer over the oxide layer. A mask is formed over the protective layer thereby forming exposed and covered regions of the protective layer. The exposed portions of the protective layer are removed to form at least first, second, and third disconnected protective structures, wherein the distance between the first and second protective structures is smaller than the distance between the second and third protective structures. The oxide layer and a portion of the substrate between the protective structures is removed to expose a portion of the substrate. A blanket polycrystalline silicon (poly) layer is formed over the substrate, and the poly layer is isotropically etched to remove the poly from between the second and third protective structures and to leave a portion of the poly between the first and second structures.

Abstract: An apparatus for measuring and correcting the straightness of a hollow vacuum nozzle for semiconductor assembly equipment comprises a collet which can rotate over 360.degree. and holds the nozzle. An indicator, such as a dial indicator, has a tip which conformally and continuously engages the nozzle so that as the collet and nozzle are rotated the indicator tip rides on the nozzle. Any horizontal movement of a bent nozzle is shown on the indicator. The bend in the nozzle can then be repaired and rechecked while the nozzle is installed in the collet.

Abstract: A method and apparatus for testing a singularized semiconductor die prior to packaging the die, thereby allowing for the packaging or other use of only known good die. The apparatus employs a housing of ceramic or other workable material. Contact pads on the interior of the package are coupled to exterior leads with conductive traces. The back side of a semiconductor die to be tested is removably mounted to a lid, and the bond pads on the die are aligned with the contact pads on the interior of the package. The lid is attached to the package thereby electrically coupling the contact pads with the bond pads on the die. Since the package has conventional exterior form and function the package is operational as a functioning device.

Abstract: A programming method for flash erasable programmable memory devices (flash EPROMs) comprises a first step of erasing the array of cells, then applying a control gate voltage to access a number of control gates. Any number of control gates can be accessed, but accessing four or eight control gates may have advantages. Regardless of the number of control gates accessed, a digit line voltage is applied to access one of the digit lines, which activates a number of cells. The digit line voltage is sensed for a voltage drop, which indicates the presence of at least one over-erased activated cell. If a digit line voltage drop is detected, a sense voltage is applied to each of the activated cells to determine which is over-erased. A heal voltage is applied to the over-erased cell for an interval of time to store electrons on the floating gate of the over-erased cell.

Abstract: A process used during the formation of a semiconductor device comprises the formation of a stack having a substrate, a layer of oxide, a polycrystalline silicon layer, and a photoresist mask. An etch is performed to pattern the polycrystalline silicon layer, then the photoresist is flowed to cover the edges of the polycrystalline silicon. Finally, a doping step is performed using the flowed photoresist as a doping barrier, thus allowing for a distance between the poly and an implanted region in the substrate.

Abstract: A sorter for orienting integrated circuit devices comprises first, second, and third sections. The first section receives the devices and sorts them into those with a leads down orientation and those with a leads up orientation. The first section comprises two opposing faces, each having a pair of lead channels. The first face lead channels receive leads of devices having a leads down orientation, and the second face lead channels receive leads of devices having a leads up orientation. The second section comprises a first channel for receiving devices from the first section having a leads down orientation, and a second channel for receiving devices from the first section having a leads up orientation. The second section further comprises an inverter integral to the second channel for inverting devices passing therethrough to a leads down orientation.

Abstract: A process for forming a thin film transistor having a lightly doped drain which is self-aligned with the transistor channel. A transistor gate is formed over a first dielectric layer, and a second dielectric layer is formed over the transistor gate. A layer of polycrystalline silicon (poly) is formed over said second dielectric layer, and the poly layer can be optionally doped with a P-type or N-type dopant to adjust the threshold voltage of the transistor. Next, an implant masking layer is formed over the gate, and has an etch mask thereupon. The exposed implant masking layer is removed, and in one embodiment the etch mask is undercut during the same etch to remove portions of the implant masking layer from under the etch mask. The exposed poly is doped with a P-type dopant. The etch mask is removed and the exposed poly is again doped with a P-type dopant to form the lightly doped drain using the implant mask to self-align the lightly doped drain with the channel region.

Abstract: Capacitors such as storage cells for Dynamic Random Access Memories are formed in a process for etching a polycrystalline silicon layer to form a storage cell during the manufacture of a semiconductor device. The etch results in a cell having reduced undercutting of the poly cell, and eliminates the formation of poly stringers. The inventive etch comprises the use of NF.sub.3 and/or SF.sub.6 during a magnetically enhanced low pressure reactive ion etch using a carbon-free etch gas of Cl.sub.2.

Abstract: A structure for a semiconductor integrated circuit device comprises a p-type transistor and an n-type transistor, with each transistor having two diffusion regions. A trench interposed between the two transistors comprises a pair of conductively doped sidewalls. One sidewall is electrically coupled with power, and the other is electrically coupled with ground. A diffusion region from each transistor is electrically coupled with one of the sidewalls, with one transistor receiving power and the other receiving ground from the conductive sidewalls. The two transistor diffusion regions not electrically coupled with one of the sidewalls are electrically interconnected.