Abstract: A method for forming a small outline "J" lead for a semiconductor device having a main body and a lead comprises three bend steps. The lead comprises a surface attached to the body, a distal end away from the body, and a proximal area interposed between the attached surface and the distal end. The method consists of the lead bend steps of rounding the distal end of the lead in a single bend step to form an are in the distal end having a radius of between 0.030" and 0.040", the arc terminating toward the proximal area of the leads in a substantially straight lead portion. Next, the proximal area of the lead is bent close to the attached surface such that the proximal area of the lead forms an angle of between about 60.degree. and 90.degree. with the attached surface of the lead. Finally, the arc in the distal end is increased to a radius of between about 0.035" and 0.045".

Abstract: The invention comprises a semiconductor package which allows pinouts and bond options to be customized after the encasement of a die in plastic, ceramic, or other suitable materials. A first embodiment of the invention has a first assembly comprising an encapsulated die having bond pads connected to bond wires which terminate in exterior pad portions on the exterior of the encapsulant. Conductive paths which are part of a second assembly electrically connect with the exterior pad portions of the first assembly and pass signals to device pinouts, which can be leads or other connecting means, to an electronic device into which the module is installed. By selectively connecting the exterior pad portions of the first assembly to the connection points of the conductive paths of the second assembly, the device pinouts and bond options can be selected. To manufacture a device having different pinouts or bond options, a bottom section having a different design is used.

Abstract: A fabrication method for a PROM cell allows improved, lower voltage programming and reduced leakage of the charge from the floating gate to the substrate (channel) region. The inventive cell uses a thin gate oxide layer along with a floating gate which is lightly doped except on one edge. This edge, for example near the drain region, is heavily doped with an angled implant. The thin gate oxide functions as thick oxide under the lightly doped region, thereby preventing the leakage and high coupling between the substrate and floating gate of a conventional thin oxide layer. The thin oxide under the heavily doped areas of the floating gate functions as thin oxide, thereby allowing improved, lower voltage programming.

Abstract: A method of producing sharp points on the surface of a substrate is described. The points are useful as field emitter tips, and may also be used to collect radiant energy and for the production of micromachined objects such as micron sized gears and levers. Conventional techniques of asperity fabrication typically use an undercut of a hard mask to etch away the substrate material. This conventional method is very time specific and difficult to control. The inventive process uses a more easily controlled etch than conventional asperity fabrication techniques. The inventive process begins with a substrate highly doped with a P-type dopant such as boron which prevents an etch with KOH or other material. A hard mask is patterned over the substrate surface, and an N-type dopant, such as phosphorous or arsenic, is implanted into the substrate surface. The N-type dopant diffuses under the hard mask at a rate more easily controlled than the etch used in conventional techniques.

Abstract: A semiconductor manufacturing process for forming a sloped contact in a layer of dielectric such as oxide comprises the use of an argon etchant. After a planar oxide layer is formed over a conductor, a photoresist mask defines the etch area. The exposed oxide is etched, thereby forming a sloped sidewall and a contact to the underlying conductor. This etch also forms a corner where the sloped sidewall joins the planar surface. The slope formed in the dielectric layer at this point is noncritical. After the photoresist is removed, a second etch using an inert material such as argon, krypton, or xenon is performed. This etch removes material at the corner at a rate of up to four times the removal rate at the sidewall and the planar surface. A faceted edge is thereby formed in the dielectric layer. The material that is removed to form the facet is redeposited over a portion of the sidewall and the conductive layer, and thereby improves the slope of the contact.

Abstract: A barrier for terminating the edge of a semiconductor die such as a dynamic random access memory device is disclosed. The barrier reduces contamination of the dielectric layers such as TEOS and BPSG from mobile ions which are inherent in fabrication materials. While the barrier can be formed at many points in the die fabrication process, its formation is preferably incorporated into the Metal1 mask, thereby preventing the need for an additional mask step. The barrier, if formed with the Metal1 mask, would therefore be formed from the material of the Metal1, conventionally tungsten, a tungsten alloy, or other metals.

Abstract: A semiconductor assembly comprises a semiconductor die which is attached by a carrier material to a lead frame. The carrier material is coated on the die side with one type of adhesive and on the lead frame side with a different adhesive. The lead frame has a small surface area to connect to the carrier material, while the semiconductor die has a large surface area to connect to the carrier material. As used with one inventive embodiment, the adhesive between the die and the carrier softens at a low temperature preventing the die from cracking at elevated temperatures. The adhesive on the lead frame side of the carrier material softens at a higher temperature than the adhesive of the die side of the adhesive, thereby firmly connecting the lead frame having a small surface area to the carrier.