Abstract: A method used during the formation of a semiconductor device comprises forming a first portion of a digit line contact plug before forming storage capacitors. Subsequent to forming storage capacitors, a second portion of the digit line plug is formed to contact the first portion, then the digit line runner is formed to contact the second plug portion. A structure resulting from the process is also described.

Abstract: A method for forming an electrical contact for a semiconductor device comprises the steps of providing a semiconductor wafer section having a major surface with a plurality of conductive pads thereon and electrically coupling each pad with an elongated electrical interconnect. Next, each electrical interconnect is encased in a dielectric and the dielectric is sectioned to expose a portion of each interconnect. An inventive structure which can be formed by the inventive method is also described.

Abstract: A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate is formed which provides a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion.

Abstract: An embodiment of an inventive semiconductor device comprises an unpackaged semiconductor wafer section having a major surface with a plurality of bond pads thereon. A plurality of conductors each comprise a lead member and at least a portion formed within a matrix. The conductors are attached to the major surface of the wafer section. An electrical connection electrically couples each of the bond pads with at least one of the lead members. Sealing material is then formed to contact at least the bond pads and the lead members.

Abstract: A method used during the formation of a semiconductor device such as a flash memory device includes the steps of forming a floating gate layer over a semiconductor wafer substrate then forming a first oxide layer over the floating gate layer. An oxidation-resistant layer such as a nitride layer is formed over the first oxide layer wherein a first portion of the oxidation-resistant layer oxidizes more readily than a second portion of the oxidation-resistant layer. To accomplish this the first portion of the oxidation-resistant layer can be formed to have a higher silicon concentration than the second portion. The first portion of the oxidation-resistant layer is oxidized to form a second oxide layer and a control gate layer is formed over the second oxide layer. An in-process semiconductor device is also described.

Abstract: A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectric is formed over these conductive structures, then a portion of the first dielectric layer is removed which forms a hole in the dielectric layer to expose the second conductive structure. Subsequently, the second conductive structure is removed to leave a void or tunnel in the dielectric layer where the second conductive structure had previously existed. Finally, a second dielectric layer is provided to fill the hole but to leave the void or tunnel in the dielectric layer subsequent to the formation of the second dielectric layer. An inventive structure resulting from the inventive method is also described.

Abstract: A memory module for an electronic device is disclosed which provides means for reducing the amount of power necessary to access a desired number of data bits. This provides a design of memory modules which requires fewer DRAMs to be turned on during a read or write cycle than present module designs, thereby using much less power.

Abstract: A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly-selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.

Abstract: A method used during the manufacture of a semiconductor device comprises providing a semiconductor wafer assembly, the assembly including a plurality of unsegmented semiconductor dice. A coating layer is formed over the semiconductor wafer assembly which causes the wafer to warp, for example through a surface tension exerted on the wafer assembly by the coating layer. To reduce wafer warp a series of grooves is etched or cut into the coating layer. The grooves are believed to relieve surface tension exerted on the wafer by the coating layer. An inventive structure resulting from the method is also described.

Abstract: A method used to form a semiconductor device comprises forming a layer such as a container capacitor layer having a bottom plate layer. The bottom plate layer is formed to define a receptacle, and a rim which defines an opening to an interior of the receptacle. The bottom plate layer is formed to have a smooth texture. Subsequently, an inhibitor layer is formed on the rim of the bottom plate layer while a majority of the receptacle defined by the bottom plate layer remains free from the inhibitor. With the inhibitor layer on the rim of the bottom plate layer, at least a portion of the receptacle is converted to have a rough texture, such as to hemispherical silicon grain (HSG) polysilicon, while subsequent to the conversion the smooth texture of the rim which defines the opening to the interior of the receptacle remains. A resulting structure is also described.

Abstract: A method for forming a ruthenium metal layer comprises combining a ruthenium precursor with a measured amount of oxygen to form a ruthenium oxide layer. The ruthenium oxide is annealed in the presence of a hydrogen-rich gas to react the oxygen in the ruthenium oxide with hydrogen, which results in a ruthenium metal layer. By varying the oxygen flow rate during the formation of ruthenium oxide, a ruthenium metal layer having various degrees of smooth and rough textures can be formed.

Abstract: A floating gate memory device comprises a first conductive floating gate layer which is horizontally oriented and a second conductive floating gate layer which is predominantly vertically oriented. The second layer contacts the first layer to make electrical contact therewith and also defines a recess. A control gate is formed within the recess. Having the control gate formed in the floating gate layer recess increases the capacitive coupling between the floating and control gates thereby improving the electrical properties of the cell and allowing for a reduction in cell size while maintaining the coupling coefficient.

Abstract: A method for forming a semiconductor device comprises the steps of forming an oxide over a silicon layer, forming a blanket first nitride layer over the oxide layer and the silicon layer, and etching the first nitride layer and the oxide layer to form a sidewall from at least the oxide layer and the first nitride layer. Next, a second nitride layer is formed over the sidewall and an oxidizable layer is formed over the second nitride layer. The oxidizable and the second nitride layers are etched to form a spacer from the oxidizable layer and the second nitride layer, and the oxidizable and the silicon layers are etched.

Abstract: A method and structure for a programmable read-only memory comprises a thin gate oxide over a source region and a thick gate oxide over the drain region. A semiconductor substrate is lightly doped and has regions of thin sacrificial oxide overlying what will become the transistor channel, source, and drain, and thick field oxide. The region that will become the transistor source is protected with photoresist, and the drain region and a portion of the channel is doped, for example, with boron. The resist and sacrificial oxide is stripped, and gate oxide is formed from the exposed silicon substrate. The more heavily doped drain and channel regions oxidize at a faster rate than the lightly doped source region, and thus the gate oxide formed is thicker. Floating and control gates are formed over the channel region, covering both the thicker and thinner gate oxide.

Abstract: A Flash EPROM cell having buried source-side injection allows for low voltage programming from the source side. A cell having the inventive structure can be programmed at 4.0 V or less. The inventive cell comprises a source area which is at a lower plane than the drain region, and a program charge is transferred to the floating gate through the source-side injector. Instead of using a self-aligned high-energy n-type dopant implant at the source side to form the source side injector as used with previous cells, which can be difficult to control, etching the substrate before impurity doping allows for the controllable formation of a sharp point of doped silicon, and allows for improved programming at a lower voltage.

Abstract: A memory array for an electronic device comprises a design which requires fewer memory devices to be activated to access a plurality of data bits, thereby reducing the amount of power required to access the data bits. The design comprises the use of a plurality of memory devices, each of which has a plurality of arrays and data out lines.

Abstract: A flash memory array comprises a primary row line and a redundant row line each having memory cells therealong. A method of accessing the flash memory array comprises preprogramming all said memory cells. Next, all memory cells are erased simultaneously. Subsequently, all memory cells along the primary row line are programmed and the cells along the redundant row line are selectively programmed. The primary row line is bypassed during any read cycle.

Abstract: A structure for attaching a semiconductor wafer section to a lead frame comprises a carrier having an outside surface and an adhesive coating the carrier. Prior to use, the structure can be placed onto spools for easy shipment and storage.

Abstract: An apparatus for measuring and correcting the straightness of a hollow vacuum nozzle for semiconductor assembly equipment comprises a collet which can rotate over 360.degree. and holds the nozzle. An indicator, such as a dial indicator, has a tip which conformally and continuously engages the nozzle so that as the collet and nozzle are rotated the indicator tip rides on the nozzle. Any horizontal movement of a bent nozzle is shown on the indicator. The bend in the nozzle can then be repaired and rechecked while the nozzle is installed in the collet.

Abstract: A pallet for holding a printed circuit board comprises first and second parallel rails and third and fourth parallel rails. The third and fourth rails each have first and second ends and form an angle of between about 30.degree. and 60.degree. with the first and second rails. The first and second ends of the third and fourth rails are connected to one of the first and second rails. The pallet further comprises an attachment for securing the printed circuit board to the third and fourth rails. The angled pallet has advantages over conventional pallets as shorts and shadowing are reduced.