Abstract: A transistor comprising an active region, with source and drain electrodes formed in contact with the active region and a gate formed between the source and drain electrodes and in contact with the active region. A first spacer layer is on at least part of the surface of the active region between the gate and the drain electrode and between the gate and the source electrode. The gate comprises a generally t-shaped top portion that extends toward the source and drain electrodes. A field plate is on the spacer layer and under the overhand of at least one section of the gate top portion. The field plate is at least partially covered by a second spacer layer, with the second spacer layer on at least part of the surface of the first active layer and between the gate and the drain and between the gate and the source. At least one conductive path electrically connects the field plate to the source electrode or the gate.

Abstract: A system for digitizing the magnitude of a first parameter, which can be inferred by applying to a second parameter and digitizing the magnitude of a resulting third parameter. The circuit which applies the second parameter has an associated bias point with which the magnitude of the second parameter varies. The value of the first parameter can result in an error in the value of the second parameter which results in an error being incurred when the digitized value of the third magnitude is used to infer a digitized value of the magnitude of the first parameter. This is avoided by adjusting the bias point with each successive trial and employing a sequential-trial ADC which performs sequential comparisons between the third magnitude and respective decision thresholds, such that there is no error in the magnitude of the second parameter when the third magnitude is equal to the decision threshold for a particular trial.

Abstract: A load reduction system and method for use with memory systems which include one or more DIMMs, each of which includes a circuit arranged to buffer data bytes being written to or read from the DIMM, with the system nominally organized such that the bytes of a given data word are conveyed to the DIMMs via respective byte lanes and stored in a given rank on a given DIMM. The system is arranged such that the DRAMs that constitute a given rank are re-mapped across the available DIMMs plugged into the slots, such that a data word to be stored in a given rank is striped across the available DIMMs, thereby reducing the loading on a given byte lane that might otherwise be present. The system is preferably arranged such that any given byte lane is wired to no more than two of the DIMM slots.

Abstract: A circuit substrate has one or more active components and a plurality of passive circuit elements on a first surface. An active semiconductor device has a substrate with layers of material and a plurality of terminals. The active semiconductor device is flip-chip mounted on the circuit substrate and at least one of the terminals of the device is electrically connected to an active component on the circuit substrate. The active components on the substrate and the flip-chip mounted active semiconductor device, in combination with passive circuit elements, form preamplifiers and an output amplifier respectively. In a power switching configuration, the circuit substrate has logic control circuits on a first surface. A semiconductor transistor flip-chip mounted on the circuit substrate is electrically connected to the control circuits on the first surface to thereby control the on and off switching of the flip-chip mounted device.

Abstract: Antenna embodiments are illustrated that are particularly suited for use in aircraft navigation, identification and collision avoidance systems. An exemplary antenna embodiment operates about a center wavelength and in association with a ground plane and comprises first and second grounded, shortened, and top loaded monopoles. These monopoles are spaced apart above a ground plane and each of them includes a feed post, a shorted post, and a top load wherein the shorted post is spaced from the feed post, is coupled to the ground plane, and has a length less than one fourth of the center wavelength. In addition, the top load is coupled to the feed post and the shorted post and is configured along orthogonal minor and major axes of the top load to have a width along the minor axis and a length along the major axis that exceeds the width.

Abstract: For use with a dumbbell having a transverse connection or connections between two weights, a support structure comprising an elongated handle bar, and means associated with the transverse connection or connections providing releasably connection or connections to the two weights. A preferred clam-shell form of the invention is disclosed.

Abstract: The invention includes a method of determining a surgical patient's pelvic position and inputting that position into a computer via a tracking system, suitable for use in navigating partial or total hip replacement surgery. The patient is first aligned with anatomical reference points in relation to corresponding locating features on a patient positioner. The positions of index features on the patient positioner are then acquired via a tracking system. Based on the positions of the index features and their known relationship to the locating features, the locations of the anatomical reference features are calculated and a pelvic plane is defined therefrom. The invention also includes a surgical tool for mounting a trackable target to a human bone, suitable for fixation to a human femur. This tool includes a removable bone clamp and a releasable coupling member, integrated with said removable bone clamp.

Abstract: A method of placing screws into bone or tissue structure during a medical procedure uses a power driven screw driver, a fastener carrier with a series of fasteners temporarily attached thereto and an elongated band structure carried by the fastener carrier system for positioning and advancing the individual fasteners of the series of medical fasteners in a controlled manner to a position to receive a driving tip on the powered screw driver.

Abstract: Efficiently controlled converter system embodiments are provided to operate in different operational modes. In a first operational PWM mode, first and second transistors are switched with a feedback-controlled duty cycle to thereby realize an inductor current that maintains a system output voltage. In a second operational PFM mode, after the output voltage decays to a lower threshold over a decay time, the control and synchronous transistors are driven a sufficient number of times to raise the output voltage to an upper threshold. The systems are controlled to efficiently transition between the first and second operational modes. For example, a converter system preferably transitions to the second PFM operational mode when current peaks of the inductor current drop below a predetermined current threshold and the system preferably transitions to the first PWM operational mode when the output voltage drops to a predetermined reference voltage.

Abstract: A voltage boost circuit is driven with a clock signal CLK which toggles between voltages V1 and V2. A first MOSFET is coupled between CLK and an output node OUT, and at least one additional MOSFET is coupled between OUT and a supply voltage. The first terminal of a capacitance is coupled at its first terminal to OUT, and at its second terminal to a delay circuit arranged to toggle its output to ˜V2 or ˜V1 a predetermined amount of time after the voltage applied to the clock signal side of the first MOSFET toggles to ˜V2 or ˜V1, respectively. The capacitance is charged to ˜V2 when the voltage applied to the clock signal side of the first MOSFET toggles to ˜V2, and OUT is increased to a voltage greater than V2 when the output of the delay circuit toggles to ˜V2. The only active device junctions subjected to the boosted voltage are MOSFET well-substrate junctions, such that no active devices are overstressed.

Abstract: Clock generator embodiments are provided to generate half-rate I and Q clock signals. The generators are configured to insure fan-out limitations, to insure correct phasing at startup, to reduce the number of signal inverters in a critical path, and to reduce the total number of inverter structures to thereby substantially extend generator operational frequency. An exemplary generator embodiment requires only two tri-state inverters and four inverters. These clock generators are particularly suited for variety of electronic systems such as high speed data serializers.

Abstract: A current limit scheme for current-mode DC-DC converters. The current limit scheme is used to limit the current through the inductor during a current limit event. Current flows through the inductor alternately from first and second power devices, with one of said devices operating in the on-state while the other is in the off-state. The current through the second power device is sensed and tracked if the peak inductor current exceeds a particular value. The inductor current is regulated by modulating the on-time of the first power device that delivers current from the input voltage source to the output through the inductor. Thus, the modulator adjusts the on-time of the first power device using past and present information related to the current flowing through the second power device and the instantaneous output voltage of the converter to limit the peak inductor current from exceeding a maximum value.

Abstract: An optical tracking system comprises an array of point source emitters that output respective optical emissions, and a plurality of angle of arrival sensors. Each sensor comprises one or more optical elements and a focal plane array (FPA), with the optical elements arranged to resolve the optical emissions into one or more linear patterns on the FPA. A processing system in communication with the sensors establishes the orientation and position of each of the optical emitters using the linear patterns. A headgear tracking system employs point source emitters on a piece of headgear, with front and rear arrays of angle of arrival sensors located in an aircraft cockpit; a processing system in communication with the sensor arrays establishes an orientation and position for each of the optical emitters on the headgear.

Abstract: An LED package containing integrated circuitry for matching a power source voltage to the LED operating voltage, LEDs containing such integrated circuitry, systems containing such packages, and methods for matching the source and operating voltages are described. The integrated circuitry typically contains a power converter and a constant current circuit. The LED package may also contain other active or passive components such as pin-outs for integrated or external components, a transformer and rectifier, or a rectifier circuit. External components can include control systems for regulating the LED current level or the properties of light emitted by the LED. Integrating the power supply and current control components into the LED can provide for fabrication of relatively small LEDs using fewer and less device-specific components.

Abstract: Methods for wafer level fabricating of light emitting diode (LED) chips are disclosed with one embodiment of a method according to the present invention comprising providing a plurality of LEDs and then coating of the LEDs with a layer of first conversion material so that at least some light from the LEDs passes through the first conversion material. The light is converted to different wavelengths of light having a first conversion material emission spectrum. The LEDs are then coated with a layer of second conversion material arranged on the first layer of conversion. The second conversion material has a wavelength excitation spectrum, and at least some light from the LEDs passes through the second conversion material and is converted. The first conversion material emission spectrum does not substantially overlap with the second conversion material excitation spectrum.

Abstract: An apparatus for monitoring the pulse time of switches within a DC to DC power supply, comprising a timing circuit responsive to a switching confirmation signal to commence timing and to monitor for control signals being sent to the switch and to indicate whether elapsed period between the switching confirmation signal and the control signal is too long or too short.