Abstract: A mask set of two masks and a method of using these masks in a double exposure to avoid line shortening due to optical proximity effects is described. A pattern having pattern elements comprising a number of line segments, wherein each of the line segments has one or two free ends which are not connected to other mask pattern elements is to be transferred to a layer of resist. A first mask is formed by adding line extensions to each of the free ends of the line segments. A cutting mask is formed comprising rectangles enclosing each of the line extensions wherein one of the sides of said rectangles is coincident with the corresponding free end of said line segment. The first mask has opaque regions corresponding to the extended line segments. The cutting mask has transparent regions corresponding to the cutting pattern. In another embodiment a pattern having pattern openings comprising a number of line segments.

Abstract: A method of routing power supply voltage electrodes and reference voltage electrodes which makes efficient use of chip area, maximizes decoupling capacitance, and reduces voltage drops due to electrode resistance is described. The two top wiring layers of an integrated circuit chip are used as power distribution layers to distribute the power supply voltage and reference voltage so that the power supply voltage bus electrode and reference voltage bus electrode are in separate wiring layers. The chip is partitioned into a number of sub-blocks with spaces between the sub-blocks. In a first wiring layer the power supply voltage bus electrode is routed so as to surround each of the sub-blocks. In a second wiring layer the reference voltage bus electrode is routed so as to surround each of the sub-blocks.

Abstract: A system and method for detecting defects in integrated circuit wafers related to photolithographic processing of the wafers. The system has an image processor, or image computer, and an image memory, which has image data for production wafer types stored therein. A defect detection wafer is scanned by an objective lens and the image is detected by an image detector. The image detector data output is fed to the image processor along with image data for a selected production wafer type from the memory. The image processor feeds image data to a visual display which displays a superimposed image of the defect detection wafer and the selected production wafer type. This superimposed image makes it easier to detect actual defects in a production wafer.

Abstract: A sputter cleaning system and method are described which provide improved temperature control of the pedestal and thus of a substrate being sputter cleaned. The sputter cleaning system comprises a conducting metal pedestal to provide a conducting surface beneath a substrate being sputter processed. A cooling channel is formed in the metal pedestal. In one example the cooling channel typically is made up of a number of concentric, interconnected, circular cooling sub-channels. Other shape cooling channels, such as radial, can also be used. An inlet tube delivers a cooling liquid, such as water, to the cooling channel and an exhaust tube removes the cooling liquid from the cooling channel thereby removing heat from the pedestal. The cooling liquid removes heat from the pedestal, thereby controlling the temperature of the pedestal and the substrate undergoing sputter cleaning.

Abstract: A composite dielectric layer and method of forming the composite dielectric layer for the passivation of exposed copper in a copper damascene structure are described. The composite layer consists of a passivation dielectric layer and an etch stop dielectric layer and is formed over the exposed copper prior to the deposit of an inter-metal or final passivating dielectric layer. Via holes are etched in the inter-metal or final passivating layer and the composite dielectric layer provides an etch stop function as well as passivation for the exposed copper conductor. A thin layer of passivation dielectric, such as silicon nitride, is formed directly over the exposed copper to passivate the copper. A thin layer of etch stop dielectric, such as silicon oxynitride, is then formed over the layer of passivation dielectric. The passivation dielectric is chosen for passivation properties and adhesion between the passivation dielectric and copper. The etch stop layer is chosen for etch stop properties.

Abstract: Methods for a die to die and a die to database inspection of phase shifting masks is described. A layer of partially transmitting material, such as an anti-reflection coating, is formed on the mask covering the phase shifting mask elements. The mask is then illuminated by a light source and the light transmitted through the mask is detected. Defects in the pattern of phase shifting mask elements will cause a difference in the amount of light transmitted through the defect when compared to a defect free phase shifting mask element. This difference can be used to perform a die to die inspection or a die to database inspection of the pattern of phase shifting mask elements.

Abstract: A duty cycle correcting circuit is described having a first capacitor connected between a first node and a reference node and a second capacitor connected between a second node and the reference node. When the duty cycle of the output clock signal is greater than 50% the voltage across the second capacitor decreases thereby increasing the charging rate of the first capacitor, decreasing the discharging rate of the first capacitor, and restoring the output duty cycle to 50%. When the duty cycle of the output clock signal is less than 50% the voltage across the second capacitor increases thereby decreasing the charging rate of the first capacitor, increasing the discharging rate of the first capacitor, any restoring output duty cycle to 50%.

Abstract: A substrate and method of encapsulating a substrate based electronic package using injection molding and a two piece mold is described. The substrate has a barrier material formed on a gating region of the substrate. The barrier material can be formed directly over circuit wiring traces formed on the substrate thereby avoiding restrictions on the location of circuit wiring traces. The barrier material and encapsulant are chosen such that the adhesive force between the barrier material and the encapsulant is greater than the adhesive force between the barrier material and the substrate. When the mold runner is broken away the barrier material is also peeled away without damage to the substrate or circuit wiring traces.

Abstract: A mask pattern having an anti-ESD ring which protects the pattern region of the mask from damage due to ESD events. The anti-ESD ring has a space between two broad border regions formed of an opaque metal such as chrome. ESD fingers, or rods extend from one of the border regions to within a small gap of the other border region. These ESD fingers act as lightning rods so that ESD events preferably occur across this small gap between the ESD fingers and one of the border regions. The ESD fingers are small enough so that any metal transferred across the gap in an ESD event is very small. The gap is located so that any metal transferred is far away from the pattern region of the mask. The ESD fingers confine ESD events to a preferred region of the mask and damage to the pattern region is avoided.

Abstract: A bonded structure comprising the physical and electrical connections between an integrated circuit element and substrate using a composite bump comprised of a single polymer body of low Young's Modulus and a conductive metal coating. The bond can be formed using thermocompression bonding, ultrasonic bonding, application of heat or application of light. The bond can also be formed using a non conductive adhesive between the integrated circuit element and the substrate. The bond can also be formed with a conductive adhesive coating on the composite bump.

Abstract: A method of determining overlay accuracy, using visual inspection, of a first circuit pattern relative to a second circuit pattern. The first circuit pattern and the second circuit pattern are too large to be contained in a single reticle and are formed separately on an integrated circuit wafer and photo stitched together. A first overlay pattern is located adjacent to the first circuit pattern on a mask. A second overlay pattern is located adjacent to the second circuit pattern on a mask, preferably, but not necessarily, the same mask. The first overlay pattern and the second overlay pattern are located so that their images in the layer of developed photoresist will be adjacent to each other after the photoresist is exposed with the first and second circuit patterns and developed. Visual observation of the images of the first and second overlay patterns is then used to determine the overlay accuracy of the first circuit pattern relative to the second circuit pattern.

Abstract: A magnetic shielding element for a magnetic recording and sensing device which prevents the problem of pop-corn noise or covariance of amplitude noise in the magnetic sensing device. The shielding element has a layer of antiferromagnetic exchange material formed on a layer of single domain first ferromagnetic material. The single domain first ferromagnetic material is stabilized by the antiferromagnetic exchange material. A layer of non-magnetic metal is then formed on the layer of antiferromagnetic exchange material and a layer of second ferromagnetic material is formed on the layer of non-magnetic metal to complete the shielding element. When the single domains of the first ferromagnetic material are disturbed by the strong magnetic fields of a write cycle they relax with a relaxation time of pico seconds and are fully relaxed before a read cycle begins.

Abstract: A molded flexible circuit assembly and method of forming a molded flexible circuit assembly which use a molded stiffener, and do not require any additional type of stiffener, are described. A molded stiffener is formed on a flexible tape at the same time molded encapsulation units are formed to encapsulate circuit die which are attached to the flexible tape. The molded stiffeners provide adequate rigidity for processing of the molded flexible circuit assembly. When the stiffeners are no longer needed they are removed at the same time the mold runners are removed. No additional processing steps are required for either the formation or removal of the molded stiffeners.

Abstract: A method of forming an isolation trench structure wherein the dielectric material filling the trench extends beyond the trench edges thereby preventing gaps at the trench edges. A layer of first dielectric is formed on a silicon substrate and a layer of silicon, either polysilicon or amorphous silicon, or silicon nitride is formed on the layer of first dielectric. A resist mask having a trench opening is then formed on the layer of silicon or silicon nitride. An isotropic lateral etch, either a plasma isotropic lateral etch or a chemical wet etch, is then used to etch that part of said silicon or silicon nitride directly under the trench opening in the resist mask and to undercut the silicon or silicon nitride a first distance beyond the edge of the trench opening in the resist mask, thereby forming an oversize trench opening in the layer of silicon or silicon nitride. The trench opening is then transferred to the layer of first dielectric and a trench is formed in the silicon substrate.

Abstract: An apparatus and method for developing a selectively exposed resist pattern, on an integrated circuit wafer, which avoids damage to the resist pattern and allows greater freedom in the choice of resists. Developer is placed on a selectively exposed layer of resist for a first time. The layer of resist and developer are then immersed in a cleaning liquid for a second time to stop the developing action and remove the developer. As an option, ultrasonic power can be delivered to the wafer or the cleaning liquid while the layer of resist is immersed in the cleaning liquid. The cleaning liquid is then removed from the layer of resist, now a resist pattern, and the wafer and resist pattern is placed in a vacuum for drying.

Abstract: A method of forming self aligned contacts in silicon integrated circuit wafers which has a reduced contact resistance is described. A contact hole formed in a layer of dielectric is filled with polysilicon using a split polysilicon process. A first polysilicon layer is deposited after the contact hole is opened. The first polysilicon is preferably, but not necessarily, high temperature film doped polysilicon. The first polysilicon is then treated using C2F6/O2. A second polysilicon layer, preferably furnace doped polysilicon, is then deposited to completely fill the contact hole. The wafer is then planarized, using chemical mechanical polishing or back etching, leaving polysilicon completely filling the contact hole and forming a low resistance contact.

Abstract: A method and design for the fabrication of a laminated yoke for a high data rate magnetic read-write transducer head. A full film layer of first ferromagnetic material is formed on a base using either plating or sputtering. The base comprises a read head, a ferromagnetic pole piece, and a ferromagnetic shield which also serves as a pole piece. A patterned layer of first non-magnetic dielectric is then formed on the full film layer of first ferromagnetic material. A patterned layer of photoresist is then formed on the full film layer of first ferromagnetic material and the patterned non-magnetic dielectric and used as a frame for a frame plating deposition of a patterned layer of second ferromagnetic material. The full film layer of first ferromagnetic material and the non-magnetic dielectric are then patterned, using the patterned layer of second ferromagnetic material as a mask and ion beam etching.

Abstract: A substrate assembly and method of forming the substrate assembly having a very thin form factor and a large amount of manufacturing flexibility. A flexible tape has a number of device blocks. Devices, passive or active, are joined to the device blocks forming a flexible tape assembly and the flexible tape assembly is electrically tested. Substrates are formed having cavities matching the device blocks. The flexible tape assembly is then joined to the substrate such that the devices fit into the cavities, thereby forming a substrate assembly having a very thin form factor. The flexible tape can be stored on a reel and the substrates can be formed in an array and cut to the desired size providing manufacturing flexibility.

Abstract: An antenna is formed from two antenna elements, a first antenna element and a second antenna element, wherein the second antenna element surrounds the first antenna element. A shorting element electrically connects the inner antenna element to the outer antenna element. An insulating gap insulates the inner antenna element from the outer antenna element except for the region where the shorting element connects the two antenna elements. A coaxial cable connects the antenna to a transceiver. The inner conductor of the coaxial cable is connected to the first antenna element and the outer conductor of the coaxial cable is connected to the second antenna element. The length of the outer perimeter of the first antenna element is equal to an integral multiple of one quarter of the wavelength of the center frequency of the antenna. The inner antenna element can be rectangular, square, circular, oval, or any similar shape. More than one antenna can be formed on a single layer of dielectric material.

Abstract: A local bit switch selecting circuit and method for systems having a first number of banks of sense amplifiers with a second number of sense amplifiers in each sense amplifier bank. The bit switch selecting circuit and method use a single N channel field effect transistor in each sense amplifier bank. This provides bit switch selecting capability while significantly reducing the number of devices and chip area required.