Abstract: An antenna that can be used as an active receiving antenna and a transmitting antenna is formed by forming dual disk antenna elements. The dual disk antenna elements are formed by etching a pattern in a layer of conducting material, such as copper, formed on a substrate of dielectric material. One of the disks acts as the active antenna element and the other disk acts as a counterpoise antenna element. In one embodiment a RF amplifier chip is used to form an active receiving antenna. In another embodiment the RF amplifier chip is removed and the antenna can be used either as a receiving antenna or a transmitting antenna. In another embodiment a RF amplifier chip is used with an electronic switch to include the RF amplifier chip when the antenna is used as a receiving antenna and to switch the RF chip out of the circuit when the antenna is used as a transmitting antenna.

Abstract: A method of routing power supply voltage electrodes and reference voltage electrodes which makes efficient use of chip area, maximizes decoupling capacitance, and reduces voltage drops due to electrode resistance is described. The two top wiring layers of an integrated circuit chip are used as power distribution layers to distribute the power supply voltage and reference voltage so that the power supply voltage bus electrode and reference voltage bus electrode are in separate wiring layers. The chip is partitioned into a number of sub-blocks with spaces between the sub-blocks. In a first wiring layer the power supply voltage bus electrode is routed so as to surround each of the sub-blocks. In a second wiring layer the reference voltage bus electrode is routed so as to surround each of the sub-blocks.

Abstract: A phase shifting mask set and method of suing the phase shifting mask set to pattern a layer of negative photoresist. The mask set comprises a first phase shifting mask and a second phase shifting mask. The first phase shifting mask has regions of 90° phase shift and −90° phase shift in the contact hole regions of the mask. The second phase shift mask also has regions of 90° phase shift and −90° phase shift in the contact hole regions of the mask. In the second phase shift mask the 90° phase shift regions are rotated 90° spatially with respect to the 90° phase shift regions of the first phase shift mask and the −90° phase shift regions are rotated 90° spatially with respect to the −90° phase shift regions of the first phase shift mask. A layer of negative photoresist is exposed with the first and second phase shift masks and developed to form the photoresist pattern used to form contact holes.

Abstract: A method is described for using computer aided design data for contact holes in a background, such as an opaque background or a phase shifting background, to generate computer aided design data for fabricating a mask an outrigger pattern. The outrigger pattern mask has contact holes surrounded by a first border of opaque material and the first border of opaque material surrounded by a third border of attenuating or 100% transmittance phase shifting material. The third border of attenuating or 100% transmittance phase shifting material is surrounded by opaque material. The design data for the contact hole pattern, a background pattern, a first correction pattern, and a second correction pattern are combined in a computer processor to generate final data. The final data is used to fabricate the mask.

Abstract: A method of forming a capacitor for use in high density DRAM circuits is described. A layer of silicon dioxide over an integrated circuit wafer having devices formed therein. A contact hole, which is larger at the top of the contact hole than at the bottom of the contact hole, is formed in the layer of silicon dioxide. A layer of polysilicon is then formed on the sidewalls and bottom of the contact hole. Silicon dioxide spacers are then formed on the polysilicon formed on the sidewalls of the contact hole so that a center cavity remains in the contact hole. The center cavity is then filled with polysilicon to form a center pillar which makes electrical contact with the polysilicon at the bottom of the contact hole. The silicon dioxide spacers are then etched away. A capacitor dielectric layer of silicon dioxide is then deposited on the substrate thereby covering the polysilicon pillar in the contact hole and the polysilicon on the sidewalls and bottom of the contact hole.

Abstract: This invention describes an attenuating phase shifting mask, a method of forming the attenuating phase shifting mask, and a method of using the attenuating phase shifting mask to expose a contact hole pattern having both dense and isolated contact holes on a layer of photosensitive dielectric. The mask has a rim of first attenuating phase shifting material, having a first transmittance and providing a phase shift of 180°, surrounding the dense holes and a rim of second attenuating phase shifting material, having a second transmittance and providing a phase shift of 180°, surrounding the isolated holes. The second transmittance is greater than the first transmittance. The dense holes have a duty ratio of less than 2.0 and the isolated holes have a duty ratio of greater than or equal to 2.0.

Abstract: A method of using a monitor wafer to monitor the shielding of alignment marks during material deposition steps. The alignment marks are shielded using shielding tabs attached to the clamp ring used to clamp the wafer during deposition of a layer of material. An oxide monitor wafer, having the same size and shape of product wafers, has monitor marks formed thereon. The center of the monitor marks has the same location on the monitor wafer as the alignment marks have on the product wafers. The monitor wafer is subjected to the same processing steps as the product wafers through the step of material deposition. The clamp ring is removed from the monitor wafer and the distance from the center of the monitor marks and the edge of the deposited material is determined. The monitor marks are formed so that the distance from the center of the monitor marks and the edge of the deposited material can be determined by direct observation of the monitor marks.

Abstract: An attenuating phase shifting mask and method of forming an attenuating mask for patterns having both isolated and dense contact holes and/or line/space patterns on the same mask. In the more isolated regions of the contact hole mask the contact holes have 0° phase shift and 100% light transmission. In the dense regions of a contact hole mask the contact holes have 0° phase shift and a second thickness of light absorbing material with a relatively low light absorption. The region around the contact holes have 180° phase shift and a first thickness of light absorbing material with a relatively high light absorption. The lines of a line/space mask have 180° phase shift and a first thickness of light absorbing material with a relatively high light absorption. The spaces between the isolated lines have 0° phase shift and 100% light transmission. The spaces between the dense lines 0° phase shift and a second thickness of light absorbing material with a relatively low light absorption.

Abstract: A method of filling contact holes in a dielectric layer on an integrated circuit wafer. The method reduces processing steps and results in a reliable metal plug filling the contact hole. In one embodiment the contact hole is filled using blanket deposition of titanium silicide using chemical vapor deposition followed by etchback. In a second embodiment the contact hole is filled with titanium silicide using selective chemical vapor deposition of titanium silicide. In a third embodiment an adhesion layer of titanium silicide is formed on the sidewalls and bottoms of the contact holes. A conductor metal of titanium silicide, aluminum, tungsten, or copper is used to fill the contact hole using selective chemical vapor deposition.

Abstract: A bonded structure comprising the physical and electrical connections between an integrated circuit element and substrate using a composite bump comprised of a single polymer body of low Young's Modulus, a conductive barrier metal coating covering the polymer body and a soldering metal coating covering the conductive barrier metal coating. When the bonded structure is formed the composite bump is deformed and the low Young's Modulus of the polymer body allows a very reliable bonded structure with very low bonding force. Due to the low Young's Modulus there is little stress tending to break the solder joint after the bonded structure is formed. The bond is formed using a soldering process so that the soldering metal forms a conductive adhesive between the composite bumps and either the substrate input/output pads or the integrated circuit element input/output pads.

Abstract: A pressure sensor and method of forming the pressure sensor are described. The pressure sensor is formed by etching a number of trenches in a silicon substrate. Dielectric spacers are formed on the sidewalls of the trenches. The bottoms of the trenches are then etched using isotropic etching to undercut the sidewalls of the trenches and form a number of silicon bridges with a limited gap between the underside of the bridges and the bulk silicon substrate. A filler dielectric is then deposited to fill the gaps between the sidewalls of the trenches thereby forming a flexible membrane. Piezoresistors are formed in the silicon bridges or, alternatively, on the flexible membrane. Pressure changes deflect the flexible membrane causing resistance changes in the piezoresistors which can be monitored and related to pressure. The limited gap between the underside of the bridges and the bulk silicon substrate provides overpressure protection for the sensor.

Abstract: A method is described for applying Optical Proximity Correction to corners and line ends in a pattern having critical dimensions in the sub micron region. Segments of curves are used to approximate corners and line ends in a pattern. The normal vector to the curve and area vector are then determined for all points on the segment of the curve used to approximate the pattern feature. The area vector has the same direction as the normal vector and a magnitude equal to the distance between the curve and the undistorted pattern. An optical proximity correction vector is then determined as the sum of a first scaler function multiplied by the unit normal vector and a second scaler function multiplied by the area vector. Next an optimum optical proximity correction shape is determined by moving the curve a distance and direction equal to the optical proximity correction vector.

Abstract: A method of forming attenuating phase shifting masks having an opaque border on a mask blank having a layer of attenuating phase shifting material overlaying a transparent mask substrate, a layer of opaque material overlaying the layer of attenuating phase shifting material, and a layer of resist overlaying the layer of opaque material. First pattern regions are exposed in the resist using an electron beam and a first exposure dose. Second pattern regions surrounding each of the first pattern regions, are left unexposed providing a width of unexposed resist around each of the first pattern regions. Third pattern regions surrounding each of the second pattern regions are exposed in the resist using the same electron beam and a second exposure dose, which is less than the first exposure dose. A border region of resist around the outer periphery of the mask is not exposed.

Abstract: This invention provides a bonded structure and a method of forming the bonded structure for joining a lead array to the conducting bonding pads of an integrated circuit element. The invention uses an anisotropic conductive film with tape automated bonding to form the bonded structure. The invention provides a low cost method of tape automated bonding which uses lower temperature and pressure in the bonding process and provides a bond which is automatically encapsulated after the bonding has been completed. The lower temperature and pressure improve the dimensional stability of the elements of the bonded structure and the automatic encapsulation provides improved reliability.

Abstract: A method of fabricating a damascene structure for copper conductors. Layers of first, second, and third dielectric are formed on a silicon substrate having devices formed therein. The second dielectric will subsequently act as an etch stop. The third dielectric is a sacrificial layer used to protect the second dielectric. Contact holes are then etched in the layers of first, second, and third dielectric. A first barrier metal and a first conductor metal are then deposited filling the contact hole. The first barrier metal and first conductor metal are then removed down to a level between the original top surface of the layer of third dielectric and the top surface of the second dielectric using a method such as chemical mechanical polishing. The sacrificial third dielectric protects the layer of second dielectric during the chemical mechanical polishing. A layer of fourth dielectric is then deposited.

Abstract: A method of forming an alternative phase shifting mask and forming a circuit pattern on a wafer using the mask are described. Optical proximity correction is added to a data file, in which a description of a circuit pattern has been stored, to obtain a first modified data file. The first modified data file is then separated into a second modified data file, for regions of the mask having dense line/space patterns, and a third modified data file, for regions of the mask having isolated line space patterns. Critical dimension bias is then added to the second modified data file forming a fourth modified data file. The third modified data file and the fourth modified data file are then merged into a single fifth modified data file. The fifth modified data file is then is then converted to an alternative phase shift data file. An alternative phase shift mask is then formed from the alternative phase shift data file.

Abstract: This invention provides a multi-layer multi-phase phase shifting photomask and a method for fabricating the same. The photomask of this invention uses a number of phase shifting layers each layer providing less than 180°optical phase shift to provide a total optical phase shift of 180°. The multi-layer multi-phase phase shifting photomask provides a gradual transition form no phase shift to 180° phase shift at pattern edges thereby improving image quality. The patterns in the layers of phase shifting material are formed using non critical etching steps. The thickness of the phase shifting layers is controlled by the deposition of the layers of phase shifting material which is relatively easy to control.

Abstract: An anti-reflective coating and method of forming the anti-reflective coating are described wherein the anti-reflective coating is part of a silicon nitride layer formed on a semiconductor integrated circuit substrate. The anti-reflective coating is formed under the photoresist layer for greater effectiveness but does not disrupt the process flow since the anti-reflective coating is part of the silicon nitride layer. A first silicon nitride layer is formed having an index of refraction of about 2.1. A second silicon nitride layer having an index of refraction of about 1.9 and a second thickness is formed on the first silicon nitride layer. A layer of photoresist is then formed on the second silicon nitride layer. The second thickness is chosen to be equal to the wavelength of the light used to expose the layer of photoresist divided by the quantity of 4 multiplied by 1.9. The second silicon nitride layer acts as an effective anti-reflective layer.

Abstract: A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.

Abstract: This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits. The layout uses dummy Metal oxide field effect transistors, or MOSFETs, to keep the environment the same around each of the MOSFETs in a matched pair. The MOSFETs in a matched pair are in a single row with each MOSFET in the matched pair having dummy MOSFETs adjacent to it on either side. The dummy MOSFETs can be part of the matched pair, can be used in other parts of the circuit, or may not be used. The use of dummy MOSFETs keeps the environment around each MOSFET in the matched pair the same and this improves the matching characteristics.