Abstract: This invention provides an extended lead package and method of forming the extended lead package for electronic circuit packages. A lead frame having extended leads is used. The extended leads extend under the bottom side of an integrated circuit element or chip. The bottom side of the chip is attached to the extended leads using bonding material which is a thermal conductor and an electrical insulator. Electrical connections between the chip input/output pads and the leads are provided by wire bonds using standard wire bonding techniques. The bonding material can be a tape having adhesive on one or both sides which attaches the chip to the lead frame using mechanical pressure, and/or other means such as curing or the addition of heat. Thermal energy is removed from the package by the thermal conduction path provided by the bonding material. The completed assembly can be encapsulated using standard methods.

Abstract: A method is described for filling trenches with dielectric for shallow trench isolation which completely fills the trench and avoids problems due to dishing at the top of the trench. A trench is formed in a substrate having a second dielectric material formed thereon. The trench is lined with a third dielectric material. Sub atmospheric chemical vapor deposition, SACVD, of tetra-ethyl-ortho-silicate and ozone is used to grow a fourth dielectric on the surface of the second dielectric material and in the trench lined with the third dielectric material. The growth rate of fourth dielectric on the third dielectric is greater than the growth rate of the fourth dielectric on the second dielectric using SACVD of tetra-ethyl-ortho-silicate and ozone. The difference in growth rate assures that the trench is completely filled with fourth dielectric even for relatively thin layers of fourth dielectric grown on the second dielectric.

Abstract: A method of forming a number of closely spaced electrodes is described wherein covering the electrodes with a conformal layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition does not result in the formation of restricted regions or keyholes between adjacent electrodes. The method uses de-focussing to form the electrode mask pattern in a layer of photoresist. The focal plane in which the electrode pattern is focussed is positioned a de-focus distance above the layer of photoresist. The de-focus method results in electrodes having a trapezoidal cross section wherein the bottom of the electrode is wider than the top of the electrode. The trapezoidal cross section avoids the formation of restricted regions or keyholes when the electrodes are covered with a conformal dielectric layer, such as a layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition.

Abstract: A method is provided for cleaning exposed copper surfaces in damascene structures after chemical mechanical polishing of the copper. In a first embodiment exposed copper is annealed in a forming gas environment, a mixture of hydrogen and nitrogen, after chemical mechanical polishing, or other etching means, is used to remove the copper down to the top of the trench dielectric. A layer of silicon nitride, SiN, is then immediately deposited, preferably in situ, over the exposed copper. In a second embodiment exposed copper is subjected to a plasma of NH.sub.3 after chemical mechanical polishing, or other etching means, is used to remove the copper down to the top of the trench dielectric. A layer of silicon nitride, SiN, is then immediately deposited in situ over the exposed copper. A layer of dielectric can then be deposited on the layer of silicon nitride and processing can be continued without contaminating or oxidizing the copper.

Abstract: A mask and method of forming a mask for forming electrode patterns having both closely spaced lines and lines with greater separation between them. The mask uses a pattern formed using attenuating phase shifting material for the region of the mask with lines with greater separation and a binary pattern formed using opaque material in the region of the mask with closely spaced lines. The mask design data is used to determine the mask regions using attenuating phase shifting material and the regions of the mask using a binary pattern. The mask is illuminated using off axis illumination, preferably quadrapole off axis illumination. The mask is formed using electron beam exposure of a resist using more than one exposure dose so that only one layer of resist is required to form the two regions of the mask one using attenuating phase shifting material and one using a binary pattern.

Abstract: Device layouts are described which increase the photon current of a metal oxide semiconductor image sensor. The metal oxide semiconductor can be NMOS, PMOS, or CMOS. The key part of the photon current of the image sensors comes from the depletion region at the PN junction between the drain region and the substrate material. The layouts used significantly increase the area of this depletion region illuminated by a stream of photons. The layouts have a drain region which takes the shape of a number of parallel fingers perpendicular to the gate electrode, a number of parallel fingers parallel to the gate electrode, or a spiral. The drain regions of these layouts significantly increase the area of the drain depletion region illuminated by a stream of electrons.

Abstract: Scribeline alignment marks and a method of forming the scribeline alignment marks are provided for auxiliary alignment marks on an integrated circuit wafer. The scribeline alignment marks have the same shape and size as the contact holes formed in a layer of dielectric. The scribeline alignment marks are located in alignment rectangles in an X and Y array filling each of the alignment rectangles. Since the alignment marks have the same size and shape as the contact holes the alignment marks will not be overexposed when they are formed using a photolithographic process optimized for the contact holes. When the alignment marks are filled with metal and the wafer is planarized a step height between the top of the metal in the alignment mark hole and the dielectric allows the alignment marks to be used for automatic wafer positioning.

Abstract: A method and apparatus for inspecting photomasks having phase shifting elements which shift the phase of light but are otherwise transparent. A coherent light source is directed through a mask to be inspected, through an objective lens, through an 180.degree. phase shifting unit, and to an image divider. The coherent light source is also directed through a transparent reference substrate to the image divider. The mask to be inspected is formed on a transparent mask substrate having the same thickness and formed from the same material as the transparent reference substrate. The intensity of the light exiting the image divider is proportional to the square of the cosine of 1800 plus the phase angle between the light exiting the reference substrate and the light exiting the mask under test. The light exiting the image divider is directed to a CCD image sensor. An image computer compares the output of the CCD image sensor with an image formed from the image database and identifies defects in the mask under test.

Abstract: A method is described for removing residual metal, such as tungsten, from the edge region of a wafer. After tungsten is deposited on a wafer to fill via holes in a dielectric the wafer is planarized using Chemical Mechanical Polishing, CMP. The CMP does not remove the tungsten from the edge of the wafer. After conductor metals for a layer of conducting electrodes has been deposited a layer of photoresist is formed on the wafer and patterned to clear the metals from over the alignment marks. This photoresist is then removed from the edge region of the wafer. The residual metals are then etched away from the edge region of the wafer using the remaining photoresist as a mask during the same etching step used to remove metals from the alignment marks or during a separate etching step.

Abstract: A wafer structure and method of forming a wafer structure with all of the dielectric material and conducting material films removed from the outer periphery of the wafer in order to protect the dielectric and conducting films from damage due to wafer handling, storage, or clamping. The dielectric or conducting material is removed from the wafer edge using wafer edge exposure or edge bead rinse methods. The wafer edge exposure method is carried out at the same time the dielectric or conducting layer is being patterned.

Abstract: A composite dielectric layer and method of forming the composite dielectric layer for the passivation of exposed copper in a copper damascene structure are described. The composite layer consists of a passivation dielectric layer and an etch stop dielectric layer and is formed over the exposed copper prior to the deposit of an inter-metal or final passivating dielectric layer. Via holes are etched in the inter-metal or final passivating layer and the composite dielectric layer provides an etch stop function as well as passivation for the exposed copper conductor. A thin layer of passivation dielectric, such as silicon nitride, is formed directly over the exposed copper to passivate the copper. A thin layer of etch stop dielectric, such as silicon oxynitride, is then formed over the layer of passivation dielectric. The passivation dielectric is chosen for passivation properties and adhesion between the passivation dielectric and copper. The etch stop layer is chosen for etch stop properties.

Abstract: A molded electronic circuit package is described to which stabilizing tape can be attached using automatic or semi-automatic means. The stabilizing tape stabilizes the assembly for further processing operations such as dicing or attachment to a higher level package. The assembly comprises a substrate to which devices are attached. Molded caps are formed over the devices. Molded tape supports are formed at the same time as the molded caps and are located adjacent to opposite sides of the molded cap. The molded tape supports have the same height as the molded cap. The stabilizing tape can then be attached to the tops of the molded tape supports and the molded caps using automatic or semi-automatic means.

Abstract: A substrate assembly and method of forming the substrate assembly having a very thin form factor and a large amount of manufacturing flexibility. A flexible tape has a number of device blocks. Devices, passive or active, are joined to the device blocks forming a flexible tape assembly and the flexible tape assembly is electrically tested. Substrates are formed having cavities matching the device blocks. The flexible tape assembly is then joined to the substrate such that the devices fit into the cavities, thereby forming a substrate assembly having a very thin form factor. The flexible tape can be stored on a reel and the substrates can be formed in an array and cut to the desired size providing manufacturing flexibility.

Abstract: A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a concave top surface which intersects with the sidewalls to form a sharp edge. The cell is programmed by charging the floating gate with electrons by means of hot electron injection from the channel into the floating gate. The cell is erased by discharging the excess electrons from the floating gate into the control gate using Fowler-Nordheim tunneling. The sharp edge at the intersection of the concave top surface and the sidewalls of the floating gate produces a high electric field between the control gate and the floating gate to accomplish the Fowler-Nordheim tunneling with only moderate voltage differences between the floating gate and control gate.

Abstract: A method is described of forming phase shifting masks using a single layer of resist and a single electron beam exposure step with two different exposure doses. A layer of resist is formed on a layer of opaque material formed on a transparent mask substrate. A first pattern is exposed in the entire thickness of the layer of resist, using a first exposure dose, and a second pattern is exposed in the top portion of the layer of resist, using s second exposure dose smaller than the first exposure dose. The layer of resist is then developed and baked. The first pattern in then etched in the layer of opaque material and a first thickness of the transparent mask substrate. The first thickness of the transparent mask substrate provides a 180.degree. phase shift to light used to transfer the mask pattern to an integrated circuit wafer. Part of the layer of resist is then etched away transferring the second pattern to the resist that remains. The second pattern is then etched in the layer of opaque material.

Abstract: A composite bump structure and methods of forming the composite bump structure. The composite bump structure comprises a polymer body of relatively low Young's Modulus compared to metals covered by a conductive metal coating formed at the input/output pads of an integrated circuit element or substrate. The composite bump is formed using material deposition, lithography, and etching techniques. A layer of soldering metal can be formed on the composite bumps if this is desired for subsequent processing. A base metal pad covering the integrated circuit element input/output pad can be used to provide added flexibility in location of the composite bump. The composite bump can be formed directly on the input/output pad or on the base metal pad.

Abstract: A method of preserving alignment marks in integrated circuit substrates using shallow trench isolation after planarization using chemical mechanical polishing. A layer of silicon nitride is formed on the substrate and openings defining alignment trenches and isolation trenches are etched in the silicon nitride layer. Alignment trenches are formed in alignment regions of the substrate and isolation trenches are formed in the active region of the substrate during the same process step using the openings in the silicon nitride layer as a mask. A layer of dielectric is then deposited on the substrate filling the alignment trenches and the isolation trenches. The dielectric is then etched away from the alignment trenches and the substrate is planarized. After a layer of conducting material is deposited on the wafer the alignment trenches are preserved.

Abstract: A mask and method of forming a mask for forming a closely spaced array of contact holes and larger isolated holes in an integrated circuit wafer. The mask provides a binary mask section for the formation of the closely spaced array of contact holes where the depth of focus is not a problem thereby avoiding problems due to side lobe effect. The mask also provides a ring type attenuating phase shifting mask for the formation of isolated larger holes where improved depth of focus is required, thereby also avoiding the problems due to side lobe effect in this region.

Abstract: A method of forming an interlevel dielectric slayer of spin-on-glass is described which avoids spiral defects from occurring in the layer of spin-on-glass. Before the spin-on-glass is deposited and with the wafer spinning at a low angular velocity a first volume of isopropyl alcohol is deposited on the wafer. The wafer continues to spin at the low angular velocity for a short time. With the wafer continuing to spin at the low angular velocity a second volume, less than the first volume, of spin-on-glass is deposited on the wafer. The wafer continues to spin at the low angular velocity for a short time and then is spun at a high angular velocity for a longer time. The wafer is then removed from the apparatus used to deposit the spin-on-glass and processing of the wafer continues. Spiral defects in the layer of spin-on-glass are avoided.

Abstract: A method of programming split gate flash memory cells which avoids erroneously programming non selected cells and allows the cell size and the array size to be shrunk below previously realizable limits. For N channel cells with the control gates connected to word lines and drains connected to bit lines a negative voltage is supplied between the non selected word lines and ground potential. For P channel cells with the control gates connected to word lines and drains connected to bit lines a positive voltage is supplied between the non selected word lines and ground potential. This allows the minimum length of the control gate over the channel region to be reduced below previously allowable limits and still prevent programming of non selected cells. This also allows cell size and array size to be reduced.