Abstract: An apparatus and method for determining local de-focus problems on a real time basis in a wafer exposure system. The distance of a wafer from an objective lens and rotation of the wafer about two orthogonal axis at each field position is adjusted to achieve optimum focus for each field of the wafer. The rotational data is fed to a computer and analyzed to determine if any of the rotational angles or if the difference between individual rotational angle and the mean rotational angle exceed critical angles. If any of the critical angles are exceeded local de-focus will occur and the exposure system must be checked for defects. If none of the critical angles are exceeded processing continues with the next wafer. The comparison of the rotational angles to the critical angles is performed for each wafer before continuing with the next wafer so that problems are discovered on a real time basis.

Abstract: A method of preserving alignment marks through steps of depositing intermetal dielectric, depositing refractory metal, and planarizing the wafer is described. After deposition of a layer of first metal a layer of first intermetal dielectric is deposited on an integrated circuit wafer. The first intermetal dielectric is then etched away from the alignment region of the wafer. A layer of second metal is then deposited. A layer of second intermetal dielectric is then deposited. The layer of second intermetal dielectric is left in place in the alignment region, a layer of refractory metal is deposited, and the wafer is planarized. The refractory metal and second intermetal dielectric are then cleared from the alignment region. The second intermetal dielectric protects the alignment marks during wafer planarization. A layer of third metal can then be deposited and the alignment marks are be preserved.

Abstract: A method of forming electrical contacts between a first level electrode pattern and a second level electrode pattern through an inter-level dielectric is described. The method uses conducting metal pillars. A first level of electrodes is formed on a wafer. Conducting metal pillars are formed over the regions of the first level electrodes where contact is to be made. The conducting metal pillars are formed by depositing a layer of metal and forming the pillars using photolithographic techniques and etching. A layer of inter-level dielectric is then deposited over the conducting metal pillars and planarized thereby exposing the top surface of the pillars.

Abstract: An method and apparatus for aligning a mask to a wafer for photolithographic processing steps which does not use optical alignment. Each wafer is provided a unique identification code, such as a bar code. As wafers are processed through photolithographic steps where optical detection of an alignment mark can be easily accomplished the alignment data for each wafer is stored in a memory unit. At the next photolithographic step a detector reads the identification code and identifies the wafer being processed. The wafer identification is fed to a data processing unit which retrieves the alignment data for that wafer fro the memory unit. The data processing unit then feed alignment data to a mechanical controller which positions the wafer relative to the mask image being used in the photolithographic step.

Abstract: A method of preserving alignment marks in integrated circuit substrates using shallow trench isolation after planarization using chemical mechanical polishing. A layer of silicon nitride is formed on the substrate and openings defining alignment trenches and isolation trenches are etched in the silicon nitride layer. Alignment trenches are formed in auxiliary alignment regions of the substrate and isolation trenches are formed in the active region of the substrate during the same process step using the openings in the silicon nitride layer as a mask. A layer of dielectric is then deposited on the substrate filling the alignment trenches. The dielectric is then etched back and the substrate is planarized. That part of the silicon nitride layer in the auxiliary region of the substrate is then etched away leaving dielectric in the alignment trenches extending a step height above the substrate surface.

Abstract: A method of forming a capacitor for use in DRAM or other circuits is described. A first polysilicon node, which will form the first capacitor plate, is formed on a layer of first oxide on an integrated circuit wafer. A layer of titanium silicide is formed on the first polysilicon node by depositing titanium and reacting the titanium with the polysilicon using a first rapid thermal anneal. The titanium silicide is then agglomerated by means of a second rapid thermal anneal thereby forming titanium silicide agglomerates on the surface of the first polysilicon node with exposed first polysilicon between the titanium silicide agglomerates. The exposed first polysilicon is then etched thereby increasing the surface area of the surface of the first polysilicon node and forming a first capacitor plate. A layer of second oxide is then formed on the first capacitor plate. A patterned layer of second polysilicon is then formed on the layer of second oxide forming a second capacitor plate.

Abstract: A number of air actuated valves are added to a conventional apparatus for treating semiconductor wafers with HMDS, hexamethyl-disilazane, vapor to improve the adhesion between the wafers and resist layers. These valves allow for automatic purging of the HMDS vapor from the pipes in the apparatus by dry nitrogen thereby preventing HMDS vapor condensation in the pipes which leads to contamination of the HMDS supply. The valve system prevents any backstreaming of nitrogen gas into the HMDS supply tank.

Abstract: This invention describes a method of forming alignment marks which will be preserved after contact holes in a dielectric have been filled with barrier metal and contact metal and the wafer has been planarized. The alignment marks are formed by filling alignment lines, formed in the dielectric when the contact holes are formed, with barrier metal and contact metal. The alignment lines and contact holes are filled with metal at the same time. After the wafer has been planarized, using a method such as chemical mechanical polishing, a small thickness of the dielectric is etched back using vertical dry anisotropic etching which will not remove either the contact metal or barrier metal. This leaves barrier metal and contact metal extending above the plane of the dielectric forming alignment marks. These alignment marks are preserved after subsequent processing steps, such as deposition of a layer of electrode metal.

Abstract: A method of forming dielectric films is described wherein the low dielectric constant of a layer of dielectric material having a low dielectric constant, such as low dielectric constant spin-on-glass, is stabilized to prevent subsequent processing steps from increasing the dielectric constant. The layer of dielectric material having a low dielectric constant is treated in an inert atmosphere, such as nitrogen or argon, at an elevated temperature. This inert atmosphere treatment of the dielectric prevents the dielectric constant from increasing during subsequent processing steps.

Abstract: An apparatus for die to die inspection of masks having transparent phase shifting elements and a method of die to die inspection of masks having transparent phase shifting elements. Light from a light source is directed through a transparent mask substrate and a phase shifting mask element to a first objective lens, and through the transparent mask substrate and another phase shifting mask element to a second objective lens. Light from the first objective lens is then given a 180.degree. phase shift by a phase adjustment unit. Light from the phase adjustment unit and the second objective lens is combined at a split mirror and directed to a detector. The method makes use of the fact that the intensity of the light at the detector is proportional to the square of the cosine of one half of the phase angle between the light from the phase adjusting unit and light from the second objective lens. If the intensity of light reaching the detector is not zero, or very small, the mask has a defect.

Abstract: A method is described for filling trenches in a substrate for shallow trench isolation or for a metal damascene structure which will prevent dishing when the substrate is planarized using chemical mechanical polishing. Trenches are formed in the substrate. A layer of first material is formed on the substrate, sidewalls of the trench, and bottom of the trench. A layer of second material is then formed on the layer of first material. The substrate is then planarized using a chemical mechanical polishing. The first material, second material, and parameters of the chemical mechanical polishing are chosen so that the removal rate of the first material is greater than the removal rate of the second material. The chemical mechanical polishing then results in a planar substrate with no dishing.

Abstract: Methods for forming via holes in inter-level dielectric layers for via connections to underlying electrodes are described. The underlying electrodes do not have electrode pads or enlarged areas of the electrode to contact the conductive material in the via hole. The method avoids the problems of oversize vias and mis-aligned vias. One of the embodiments uses extra wide dielectric spacers formed in two steps on the sidewalls of the underlying electrodes. The spacers provide an effective electrode width greater than the actual width of the electrode thereby increasing the tolerance for both the size and the alignment of the via holes. Another embodiment uses alternate layers of two dielectric materials and etching methods which etch each of the two materials selectively. The dielectric material which is not etched in each step serves as an etch stop layer.

Abstract: A method of forming a rim type attenuating phase shifting mask which requires only one resist layer and developing the resist using a single developing solution. A transparent mask substrate has a layer of attenuating phase shifting material, a layer of opaque material, and a layer of resist material formed thereon. The layer of resist is exposed to a first pattern using a first exposure dose and a second pattern using a smaller second exposure dose. The resist is developed for a first time forming the first pattern in the entire layer of resist and the second pattern in the top portion of the layer of resist. The first pattern is then etched in the layer of opaque material using the first pattern in the layer of resist as a mask. In one embodiment the first pattern is then etched in the layer of attenuating phase shifting material, the resist is partially etched using an O.sub.

Abstract: This invention provides a bonded structure and a method of forming the bonded structure for joining a lead array to the conducting bonding pads of an integrated circuit element. The invention uses an anisotropic conductive film with tape automated bonding to form the bonded structure. The invention provides a method of tape automated bonding which uses lower temperature and pressure in the bonding process and provides a bond which is automatically encapsulated after the bonding has been completed.

Abstract: A method of forming shallow isolation trenches in integrated circuit wafers which prevents wafer damage due to dislocations or the like occurring at sharp corners at the intersection between the sidewalls and bottom of the trench. A trench is formed in the wafer using a series of reactive ion etching steps. The bottom of the trench is then etched using reactive ion etching with etching parameters chosen to produce dry isotropic etching. The dry isotropic etching of the bottom of the trench results in a rounded bottom and sharp corners between the sidewalls and bottom of the trench are avoided.

Abstract: A test board circuit for testing integrated circuit modules under stress conditions, such as temperature, humidity, and bias. The integrated circuit module under test is plugged into a test socket which is part of the test board circuit. Without protection electrical shorting between test socket contacts, either from improper plugging of the module under test or from the formation of conductive deposits on the socket contacts, causes erroneous results and can damage devices in the integrated circuit module under test. The test board circuit protects the devices in the integrated circuit module under test from damage due to shorting between test socket contacts and provides a voltage signal which can be used to detect when a short has occurred.

Abstract: A mask and method of systematically laying out the mask for test patterns in the frame cell region of an attenuating phase shifting mask are described. An array of sub-resolution contact holes are used in the border regions of the mask to prevent over exposure of photoresist in the regions between the device regions on a wafer due to side lobe effect. The mask and method provide for a buffer distance surrounding the features of the test patterns. The buffer distance is free of sub-resolution contact holes. When the buffer distance is correctly chosen problems due to side lobe effect at the frame cell portion of the mask are prevented.

Abstract: A method of forming buried contacts in MOSFET and CMOS devices which substantially reduces the depth of the buried contact trench. A split polysilicon process is used to form the gate electrode and contact electrode. The first polysilicon layer is very thin layer of undoped polysilicon, having a thickness of less than 100 Angstroms. The second polysilicon layer is a layer of doped polysilicon having a thickness of between about 950 and 1150 Angstroms. The buried contact can be formed either using ion implantation or diffusion of impurities from the layer of doped second polysilicon into the contact region. When the metal layers are etched to form the gate electrode and contact electrode the resulting buried contact trench is less than 500 Angstroms deep.

Abstract: An integrated de-focus pattern provides an effective in-line monitor for photo processing steps of integrated circuit wafers. The de-focus pattern is formed on an integrated circuit wafer in the vertical and horizontal spaces between integrated circuit chips. The de-focus pattern has a number of different test patterns at different heights above the wafer surface. De-focus patterns are placed across the entire wafer surface. The de-focus patterns are formed at the same time the features of the circuit chips are formed. The de-focus patterns can be analyzed optically or using a scanning electron microscope.

Abstract: An attenuating phase shifting photomask is formed using attenuating phase shifting composite material combining the optical properties of a first material having a high extinction coefficient and a second material having a high index of refraction. The first material is LaNiO.sub.3 and the second material is either TiO.sub.2 or Ta.sub.2 O.sub.5. The first and second materials are combined to produce composites of either (LaNiO.sub.3).sub.x (TiO.sub.2).sub.1-x or (LaNiO.sub.3).sub.x (Ta.sub.2 O.sub.5).sub.1-x to form attenuating phase shifting blanks and masks. Co-deposition of LaNiO.sub.3 and either TiO.sub.2 or Ta.sub.2 O.sub.5 uses rf-magnetron sputtering to form the (LaNiO.sub.3).sub.x (TiO.sub.2).sub.1-x or (LaNiO.sub.3).sub.x (Ta.sub.2 O.sub.5).sub.1-x films on a transparent quartz substrate.