Abstract: A method and apparatus for confirming the operation of memory (212) operates during periods when the memory is not operating in a standard execution mode. This strategy allows the memory to be checked real-time without impacting normal bandwidth of an associated CPU (200). The method and apparatus guarantees deterministic testing by including circuitry and steps which force bus mastership and, therefore, memory access if the memory is busy for too long a period of time.

Abstract: A data processor (102) includes a first-in, first-out (FIFO) buffer (110) having a variable threshold. The FIFO buffer (110) has a plurality of entries (200) for storing at least a portion of a data block that is to be transmitted through the FIFO buffer (110). To allow data blocks of varying size to be transmitted at different data rates, a variable threshold value for determining a maximum fullness of the FIFO buffer (110) is automatically calculated by the data processor (102) for each data block. This allows the data block to be transmitted through the FIFO buffer (110) as a continuous data stream, without interruption, from the data processor (102) to a data consumer. The variable threshold value is appended to a first entry of the data block along with start bits to indicate a beginning of the data block. The FIFO buffer (110) may include read and write counters (208, 212) and a comparator (210) for comparing a difference between read and write pointers and the variable threshold value.

Abstract: A BIST controller (112) and methodology uses the DRAM controller (108) refresh signals to test the data retention characteristics of a DRAM memory array (132). The BIST controller blocks a fraction of the refresh cycles generated by the DRAM controller to provide a margin of confidence above the DRAM's specified retention time. The BIST controller is especially suited to embedded applications in which access to the memory is indirect and to applications in which the memory system is modular. The invention may also be used to characterize the actual retention time of a particular DRAM allowing the system to optimize the DRAM's refresh interval.

Abstract: A method and apparatus for performing mis-aligned read and write operations to a stack involves providing a memory array (110). The memory array is split into a high byte memory array (116) and a low byte memory array (112). Each memory array (112 and 116) has its own bus interface unit (114 and 118) respectively. The high byte bus interface unit (118) increments the address bits to the high byte memory array (116) on every access to compensate for mis-aligned data. However, the low byte bus interface unit (114) does not increment the address value before accessing the memory array (112). By doing so, memory is read from the memory arrays (112 and 116) in either 8 bit sizes or 16 bit sizes regardless of whether the stack structure implemented in memory array (112 and/or 116) contains aligned data or mis-aligned data.

Abstract: A microcontroller (100) has a CPU (102) and memory (104). Memory (104) contains a memory array (200). A large portion of the array (200) is used to contain functional data for the CPU (102), but the array (200) also contains one or a few rows of memory content parity information. Once the array (200) is written with lasting data and/or software, a parity controller (208) will generate initial parity values which correlate to the contents of the memory array (200). This parity information is stored within the parity portion of the array (200). After generating the initial parity data, the parity controller (208) occasionally, upon some parity checking event, generates current parity from the data stored within the array (200). This current parity is compared against the parity portion of the array (200) using the parity logic (210). If errors are detected, it is clear that the software/data that was intended to be static and non-changing has experienced a leakage error, soft error event, electrical short, etc.

Abstract: An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224,226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an external voltage which is outside a predetermined voltage range, the protection circuit adjusts the voltage on the control gate of a transistor (224) in the output drive circuit. The protection circuit maintains the voltage across the transistor within the tolerance of the transistor. In one embodiment, the output drive circuit has pullup (204) and pulldown (206) portions. The output buffer provides a high voltage output driver having low voltage devices.

Abstract: A thermal sensing element (10) incorporates a vertical pnp bipolar transistor (12) whose BETA is dependent on temperature. This known relationship can be used to build a temperature sensor (200, 300), that is inexpensive, reliable, and whose process variance is predictable.

Abstract: Fuses and detect circuits (124) in an integrated circuit memory (100) include a copper fuse (208) and a fuse state detect stage (202) for detecting the open circuit state or the closed circuit state of the fuse (208). The fuse detect circuit (124) provides an output signal corresponding to the state of the fuse and during detecting, limits a voltage drop across the fuse to an absolute value independent of a power supply voltage applied to the integrated circuit memory. The fuse detect circuit (124) operates at power up of the integrated circuit memory (100) and is disabled after the state of the fuse is detected and latched, and the power supply is sufficient for reliable operation of the integrated circuit memory (100). By limiting the voltage drop across a blown copper fuse (208), a potential electro-migration problem is reduced.

Abstract: A multi-chip assembly (100) uses a clip (110) to retain multiple integrated circuits (124-130) to an assembly substrate (140). The use of a thermal medium between the integrated circuits and the heat sinks (120, 122) allows the assembly to be disassembled for rework purposes. The clip contains edge clamps (112), alignment rails (114), and alignment features (116, 316, 416) to properly orient the clip, heat sink, integrated circuits, and assembly substrate.

Abstract: A simulation monitor (502) automatically generates a monitor file (510) from a static timer output file (504). The monitor file instantiates a function, a firing equation, that triggers if and only if a critical timing path also triggers. The monitor file is written in a high level language description, suitable for efficient simulation. The test vectors which trigger the firing equation can thereby be monitored and used for hardware test at a later time. The invention may be extended to monitor other conditions of interest.

Abstract: An electrostatic discharge (ESD) discharge circuit provides robust protection to an integrated circuit (13). In one embodiment, a resistive element (71) ensures that current shunting bipolar devices (60, 62, and 68) turn-on before devices within the integrated circuit are damaged by secondary breakdown. In another embodiment, a two terminal device (69) provides base current to a bipolar device (60) that shunts excess charge. This two terminal device enters gate aided junction breakdown as does an N-type MOSFET (72 and 74) but does not exhibit the same snap-back characteristics during ESD. Consequently, the two terminal device ensures that the ESD circuit tracks process modifications to the integrated circuit.

Abstract: A segmented bus architecture (800) removes certain ESD circuitry from each I/O pad cell (806, 812) and places it in a power pad cell (808, 814) or in some other unused area of the integrated circuit which incorporates the SBA. The removed ESD circuit is shared by several adjacent I/O pad cells via a segmented ESD bus. As a result, each individual I/O pad cell may be reduced in size.

Abstract: A data processor (10) incorporates instruction regulating or "throttling" circuitry (31) for limiting consumed power. A user visible register maintains an INTERVAL field by which instruction fetch from an instruction cache (14) is periodically delayed. This INTERVAL field may be adjusted to suit the power budget of the data processor.

Abstract: A method for testing a bumped semiconductor die (14) is accomplished without excessively deforming the conductive bumps (200). In one form, testing is accomplished using a test contactor (12) which includes a deformable layer (204), such as an elastomer, which is patterned to include a plurality of openings (202) corresponding in pattern to the conductive bumps (200). The die is positioned next to the test contactor and the two are compressed together. The walls of the openings in the elastomeric material constrain the deformation of the conductive bumps in the X-Y plane due to the lateral pressure exerted on the sides of the conductive bumps. In a second form, a mechanical standoff (216) limits the extent to which the die and the test contactor can approach, thereby limiting the deformation in the Z-axis. In a third form, both elastomeric material and mechanical standoff act to constrain the deformation in the X-, Y-, and Z- axes.

Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.

Abstract: An apparatus connects a data processing system (10) with an analog telephone line and/or an ISDN line. The apparatus modulates and demodulates data from the data processing system (10) to either of the two different telephone protocols without adding unnecessary expense or noise to the system.

Abstract: A circuit and method is provided for implementing a content addressable memory circuit (100) in which an output word is produced which corresponds to the content of a reference word containing an ATM header. According to a first aspect, a binary search logic circuit (104) binarily searches the memory array (101) to find a match word whose content is equal to that of the reference word. Output signals indicate either that a match has been found or that the binary searching of the memory array (101) should continue at addresses either above or below the location address of the match word. According to a second aspect, the content addressable memory circuit (100) performs a concurrent search of switching identifiers, virtual circuit identifiers and virtual path identifiers, to determine if a virtual path connection or virtual circuit connection exists for an ATM header.

Abstract: Output buffer (100) translates input signals from one voltage range to a second voltage range. The second voltage range may be identical to the first range or may be greater. The particular range is programmable by one of several ways. This feature makes output buffer especially suitable for use in devices which must be compatible with two voltage ranges. Output buffer uses a bias generator (110) to limit the voltage across the gate oxide of its various transistors to a level which is consistent with the first voltage range.

Abstract: An electrostatic discharge (ESD) circuit (700) provides robust protection to an input/output driver circuit (10). The discharge path is provided by a bipolar transistor (202). The bipolar device is triggered by a combination of an n-type MOSFET (702), a string of diodes (200), and a biasing circuit (704). The trigger point of the MOSFET is programmable by varying the number of individual diodes in the string of diodes. The relatively high transconductance of the n-type MOSFET allows the use of a smaller ESD circuit for a given degree of protection.

Abstract: An electrostatic discharge (ESD) circuit (12) provides robust protection to an input/output driver circuit (10). The discharge path is provided by a parasitic bipolar transistor (202). The parasitic bipolar device is triggered by a combination of a MOSFET (204) and a string of diodes (200). The trigger point of the MOSFET is programmable by varying the number of individual diodes in the string of diodes. A feedback circuit (602) ensures that MOSFET (204) is in a conductive state independent of the voltage state of the voltage supply, VDD, during an ESD event.