Abstract: A data processor (10) has an execution unit (18, 20) for generating the address of each requested data double-word. The data processor fetches the entire memory line, four double-words of data, containing the requested double-word when the requested double-word is not found in the data processor's memory cache. The data processor ultimately stores the requested data in the memory cache (40) when returned from an external memory system. The data processor also has forwarding circuitry (48, 50) for forwarding previously requested double-words directly to the execution unit under certain circumstances. The forwarding circuitry will forward a requested double-word if the data processor has not crossed a memory line boundary since the last memory cache miss and if the two least significant bits of the requested and received double-words logically match.

Abstract: A data processor (10) has a branch and link address cache ("BLAC") (40) and a BTAC (48) for storing a number of recently encountered fetch address-target address pairs. The BLAC buffers data pairs identifying corresponding subroutine call and subroutine return instructions each time data processor executes a particular subroutine. Upon the second call of the subroutine, control logic (44) stores the half of the data pair identifying the subroutine return instruction and data identifying the return address in the BTAC. The data processor is thereby able to predict the target address of a subroutine return instruction as it is able to predict the target address of traditional branch instructions.

Abstract: A CAM/SRAM structure (44) performs address translations that are compatible with a segmentation/paging addressing scheme yet require only a single look-up step. Each entry in the effective-to-real-address-translator (ERAT) has two CAM fields (ESID, EPI) that independently compare an input segment identifier and an input page identifier to a stored segment identifier and a stored page identifier, respectively. The ERAT outputs a stored real address field (DATA) associated with a stored segment-stored page pair if both comparisons are equivalent. The ERAT can invalidate stored translations on the basis of segment or page granularity by requiring either a segment or a page CAM field match, respectively, during an invalidate operation.

Abstract: A data processor (12) has a branch prediction unit (28) that predicts conditional branch instructions and a control unit (70) therein that monitors the number of unresolved branch instructions. This control unit selectively allows the data processor to fetch the instructions indicated by the branch prediction unit from an external memory system depending upon the number of unresolved branch instructions. The particular threshold number of unresolved branch instructions is user programmable. The data processor thereby limits its bus accesses to those occasions when it is reasonably sure that it will need the indicated instructions.

Abstract: A testable memory array (34) has a plurality of TAG-DATA field pairs. Each TAG asserts a MATCHLINE signal if an input tag matches a stored tag. During normal operation, the asserted matchline signal causes the entry to outputs its DATA field. During a testing mode, testing circuitry (50 and 52) gates the matchline signal with the output of a one-of-N decoder (48). Consequently, only one of the various matchline signals can be asserted at any given time regardless of whether test data creates multiple tag matches. The various TAG bit cells can then be connected in scan chains without risk of driving two different DATA FIELDS to the same output bit line.

Abstract: A memory cache (14) has a semi-associative cache array (50), a cache reload buffer (40), and a cache reload buffer driver (42). The memory cache writes received data to the cache reload buffer and waits until the data is requested again before it invalidates any cache aliased entries in the semi-associative cache array. This invalidation step requires no dedicated cycle but instead is a result of the memory cache being able to simultaneously read from the semi-associative cache array and the cache reload buffer.

Abstract: A data processor (10) has a translation lookaside buffer, a "TLB," (56) for translating internal effective addresses into external real addresses. A user programmable bit in a special purpose register (68) controls which TLB entry in a group of entries will be replaced after an unsuccessful translation. Normally, the data processor uses a hardware controlled algorithm to select an entry for replacement. However, the user can overwrite the value in the special purpose register to force a certain replacement scheme. The user can thereby protect certain important translation mappings or deterministically test the TLB after manufacture.

Abstract: An address translator (42) with a by-pass circuit (106) translates a received effective address into a real address in a first mode of operation by matching a portion of the effective address and a stored translation tag. The address translator outputs a real address corresponding to the matching translation tag on a plurality of bit lines (BIT LINE). The by-pass circuit connects the input effective address to the bit lines in a second mode of operation. The address translator thereby eliminates the need for a subsequent two-to-one multiplexer.

Abstract: The disclosed data processor (10) has a future file (60) for providing the most recent value of a set of architectural registers (32, 36) to the various execution units (20, 22, 24, 26, 28, 30) of the data processor. The most recent value of the set of architectural registers is determined with respect to the original instruction sequence. The future file provides a single source for operand look-up at instruction dispatch and can be corrected in a single cycle in the event of an exception condition.

Abstract: A CAM/SRAM structure (42) performs address translations of variable length blocks, a "block address translator." Each address translation is stored in a register broken into an upper half and a lower half. The upper half contains CAM bit cells (56) which match an input effective address to a stored tag (BEPI) alternating with SRAM bit cells which store a block length tag (BL). The block length tag defines the length of the translated block and, hence, the number of bits which must match between the input effective address and the stored tag. The lower half contains SRAM bit cells which store a real address associated with the tag (BRPN) alternating with multiplexer circuits. In the event of a CAM match, each multiplexer circuit outputs either a real address bit or an input effective address bit, depending upon the block length tag. The two halves of each register are fabricated adjacent to each other in parallel rows to minimize routing requirements and reduce overall circuit capacitance.

Abstract: A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. Each pair also includes an offset tag identifying which one of a plurality of instructions indexed by the fetch address generated the entry. A branch unit (20) generates an execution address that depends upon one of the plurality of instructions. After executing each instruction, the branch unit may delete an entry from the BTAC if the instruction's execution address differs from the target address and if the instruction is the same instruction which generated the BTAC entry initially.

Abstract: An address translator (126) translates addresses, acting like a register file or a table, as necessary. The address translator contains a number of entries for matching an input address to a stored tag. An entry outputs a stored translated address if its stored tag matches the input address. A decoder (138) selects a particular entry in which to store an input translated address when the address translator operates as a register file. In these cases, a register number is also stored in the particular entry's as the entry's tag. Later, when it is necessary to read the particular entry, the register number is compared to each entry's tag to find a match. The disclosed address translator is compatible with both hardware and software refill algorithms ("tablewalks") without impacting its critical read speed path.

Abstract: A sense amplifier (10) has a pair of cross-coupled latches (12, 14, 16, 18) connected between a first voltage supply (V.sub.DD) and the sources of two transistors (20, 22). The gates of the two transistors receive a voltage differential to be sensed. The drains of the two transistors are coupled to a second voltage supply (V.sub.SS) through an enabling transistor (24). The resulting sense amplifier is fast, small, and relatively simple to construct.

Abstract: A data processor has first calculation circuitry (26), a rename buffer (34), and a queue (36). The first calculation circuitry generates a first and a second result from supplied operands and received programmed instructions. The rename buffer is coupled to the first calculation circuitry and stores a series of first results received from the first calculation circuitry. The rename buffer outputs the series of first results to a first predetermined register. The queue is also coupled to the first calculation circuitry and stores a series of second results. The queue outputs the sequence of second results to a second predetermined register in the same the sequence as it received the second results from the first calculation circuitry.

Abstract: A memory cache (14) has a plurality of cache lines (50) for storing a series of contiguous memory elements. Each series of memory elements are interlaced within the corresponding cache line on a element-by-element basis and on a bit-by-bit basis. This storage strategy allows the memory cache to output a subset memory elements within a cache line quickly and in the original contiguous order. The invention may be advantageously incorporated in an instruction cache of superscalar data processor to provide a series of sequential instructions for execution.

Abstract: A data processor has a plurality of execution units (12), a rename buffer (14) coupled to at least one of the execution units and a plurality of architectural registers (16) coupled to at least one execution unit and to the rename buffer. The rename buffer periodically receives and stores the result and periodically receives requests for the operand. Each received result and operand is associated with an architectural register. The rename buffer periodically forwards one of a set of received results to an execution unit. Each received result of the set is associated with the same architectural register. The rename buffer is operable to determine which entry is the most recently allocated among several that will update the same architectural register. This ability to both manage results destined for the same architectural register and to forward only the appropriate value increases data processor throughput and reduces instruction stalls.

Abstract: A voltage controlled oscillator (VCO) 16 generates a periodic clock signal without the use any resistors. Therefore, the described VCO may be advantageously incorporated into devices fabricated with semiconductor processes without special resistor-base design constraints.

Abstract: A pointer (86) has generate circuitry (90), propagate circuitry (90), carry circuitry (90) and detector circuitry (92). The pointer is for use with a buffer to designate one of a plurality of entries of the buffer. The generate circuitry receives a first and a second data word and generates a plurality of local generate functions. One bit of the first data word, second data word, and one of the local generate functions each corresponds to one of the entries of the buffer. Each data bit of the first data word is representative of the eligibility of the pointer to designate an entry. The second data word is representative of the pointer location at a previous time. The propagate circuitry receives the first and second data words and generates a plurality of local propagate functions. Each local propagate function corresponds to one of the entries of the buffer. The carry circuitry is coupled to the generate circuitry and to the propagate circuitry and generates a plurality of carry bits.

Abstract: A phase locked loop (10) has a first (24) and a second (28) feedback path by which a generated clock signal may be phase and frequency matched to an input reference clock signal. The two feedback paths are delay matched so either one may be used to maintain "PLL lock." However, the first path consumes significantly less power than the second path. Control circuitry (22) selects which path is fed back through a multiplexer (126) and disables the second path when the path is not needed.

Abstract: A data synchronization system (12) for use with a first and a second device has control circuitry (34), first circuitry (36, 38, 40, 42 and 44) and second circuitry (32). The control circuitry generates a first and a second control signal. The logic states of the two control signals depend upon the ratio of the clock frequencies of the two devices. The first circuitry receives a first data signal from the first device and generates a first output signal for the second device depending upon the logic state of the first control signal. Conversely, the second circuitry receives a second data signal from the second device and generates a second output signal for the first device depending upon the logic state of the second control signal. The synchronization system may be incorporated into data processing systems in which the data processor and bus operate at different clock frequencies.