Abstract: A circuit and method is provided for implementing a content addressable memory circuit (100) in which at least one output word is produced which corresponds to the content of a match word. A binary search logic circuit (103) binarily searches the memory array (101) to find a match entry with multiple words whose content is equal to that of an input value with multiple words. The amount of words in each match entry is user programmable and defined at startup. The CAM (100) is capable of masking out words to be compared or outputted and allows overlapping of words to be compared and outputted. Output signals indicate whether a match has been found.

Abstract: A method and apparatus observes a mode register (102) in a synchronous memory device. A multiplexer (306) selects the value of the mode register (102) or the conventional data path of the memory array (302) through the output buffer. The invention outputs the stored value of the control register (102) on output pins, such as address pins when no signal is expected. The multiplexer (306) maybe responsive to a variety of control signals.

Abstract: A modular switch element (12) is programmable to operate in conjunction with varying numbers of other modular switch elements in a shared memory switch fabric (10). A single modular switch element type can be used to construct a range of shared memory switch fabrics operable over a wide range of bandwidth requirements.

Abstract: A method (600, 700) and apparatus (402) for controlling a memory device, such as a synchronous dynamic random access memory (404), includes a user-programmable register containing a new parameter, PRECHARGE DELAY TIME. A memory controller (402) uses the parameter to set a minimum limit through which each page is kept open after an initial access. Subsequent access to the same page cause the controller to reset the limit, thereby extending the open page. Accesses to different pages, refresh operations, and maximum row address strobe parameters can force the page closed. A user can tune the PRECHARGE DELAY TIME to keep pages open through the time period in which it is likely that additional accesses will be to the same page. Conversely, open pages can be closed after that time period is exceeded. In both cases, the memory device will be ready for a subsequent access with minimum latency.

Abstract: A temperature sensor (1800) incorporates two diodes (1802, 1804). The voltage difference across each diode is a linear function of temperature. The voltage difference between the two diodes is also a function of the ratio of their respective sizes. These relationships can be used to build a sensor that is inexpensive, reliable, and whose process variance is predictable.

Abstract: A microprocessor (5) including a clock domain translation circuit (50a) for communicating a digital signal from a high speed clock domain to a low speed clock domain is disclosed. The disclosed microprocessor (5) includes clock generation circuitry (20) which generates internal and bus clocks at different multiples of a system clock signal. The clock generation circuitry (20) includes a counter (60) that indicates, for a given frequency ratio, signals (REGION) indicating the current phase region of the faster clock (PCLK) relative to the slower clock (BCLK). The clock domain translation circuit (50a) includes a series of input registers (82, 84) in sequence, with the output of each as well as the input signal line (IN PCLK) coupled to inputs of a multiplexer (80).

Abstract: An electronic apparatus (24, 25, 27) having a plurality of externally selectable operating states is controlled to assume sequentially those states. The control is accomplished (41, 43, 45) using a sequence of state codes which define a reflected code.

Abstract: A data processing system (10) includes a register bit structure (27) which can be hard-wired (37, 39) but is also selectively configureable for read/write operation.

Abstract: A cache memory uses content-addressable tag-compare arrays (CAM) to determine if a match occurs. In a semi-associative instruction cache, with the CAM and eight cache lines grouped together to form camlets, a binary index is used to address one camlet in the cache array, and the effective address tag match is used to select a potential line within the camlet in accessing data stored in the cache array. Since an E-tag match causes that cache line's wordline to activate, proper cache operation requires that no two (or more) E-tags within a camlet have the same match criteria (ECAM entry); the invalidation of entries is done to prevent this from happening. Due to the mapping of the effective address into the E-tag CAM and the camlet binary index, addresses that are 1-Meg apart point to the same camlet and have the same ECAM tag. The method thus employs a semi-associative cache having cache lines configured in camlets of, for example, eight lines per camlet.

Abstract: A data processor (10) has a branch and link address cache (.sup.++ BLAC.sup.++) (40) and a Branch Target Address Cache (BTAC) (48) for storing a number of recently encountered fetch address-target address pairs. The BLAC buffers data pairs identifying corresponding subroutine call and subroutine return instructions each time data processor executes a particular subroutine. Upon the second call of the subroutine, control logic (44) stores the half of the data pair identifying the subroutine return instruction and data identifying the return address in the BTAC. The data processor is thereby able to predict the target address of a subroutine return instruction as it is able to predict the target address of traditional branch instructions.

Abstract: A fully associative address translator which includes a number of entries, each of said number of entries translating a received effective address into a real address, each received effective address including a segment identifier and a page identifier. Each of the entries within the fully associative address translator includes a first translation from an effective address segment identifier into a virtual address segment identifier and a second translation from a virtual address page identifier to a real address page identifier.

Abstract: A method of requesting data in a data processing system has the steps of receiving a plurality of requests for data by a request arbitrator (12) from a plurality of requesters (REQUESTER A, REQUESTER B, REQUESTER C), requesting a first portion of each request at a first time and requesting a second portion of each request at a second time. Each of the requests for data corresponds to a first portion of data. At least one of the requests also corresponds to a second portion of data. The first portions and second portion are requested according to a first and to a second predetermined order, respectively. The disclosed method requests a critical mount of data first for each request before any non-critical data portions are requested.

Abstract: The disclosed data processor (10) dispatches load/store multiple and load/store string instructions to a load/store unit (28) as a sequence of simple load or store instructions. The sequencer unit (18) assigns an entry of a rename buffer (34) to which the load/store unit writes back the data of each simple load instruction. This strategy facilitates early data forwarding for subsequent instructions. Conversely, the sequencer unit supplies a rename buffer tag to the load/store unit if it is not able to supply the operands of a simple store instruction.

Abstract: An arbitration protocol (68) comprises the steps of receiving a first (70) and a second (74) plurality of resource request signals, and either, granting the shared resource to a selected one of a first plurality of resource users (72) or granting the shared resource to a selected one of a second plurality of resource users (76). A differing one of each of a first plurality of resource users and of each of a second plurality of resource users generates a differing one of the first plurality of resource request signals and a differing one of the second plurality of resource request signals, respectively. Each one of the first and the second plurality of resource request signals corresponds to a first logic state if a particular one of the first or second plurality of resource users requests use of a shared resource.

Abstract: A CAM system (2) stores a plurality of data sets in a plurality of pairs of CAM cells (4) and RAM cells (6). The portion of a particular data set stored in one of the RAM cells is accessed by inputting a tag to CAM cells that matches the portion of the data set stored in the CAM cell associated with the particular RAM cell. CAM system incorporates a novel two-stage matchline re-coding scheme to improve performance. Each of a plurality of first stage circuits (10) receives a plurality of matchline signals from a plurality of CAM sets and a plurality of data inputs from the corresponding RAM sets. Each output of the first stage circuits is further processed by a second stage circuit (12) which generates the final data output. The CAM system avoids the use of self-timed control signals and sense amplifiers.

Abstract: A method of loading a particular block of instructions into the instruction cache (14) of a Harvard architecture data processor (10) involves repetitively mis-predicting a branch instruction in a loop. The branch instruction is conditioned upon an instruction whose execution is contrived to output a sequential fetch address. However, the instruction's result is not available until after the branch instruction begins executing. Therefore, the data processor speculatively executes or predicts the branch instruction. In this case, the branch instruction predicts that it will branch to the particular block of instructions. The data processor then loads the instructions into its instruction cache. Later, the data processor determines that it mis-predicted the branch instruction, returning to the loop for another iteration.

Abstract: A memory cache interface (12) serially accesses each way in an M-way set asociative memory cache (11) when it performs a read operation. The memory cache returns a data quantum and a tag corresponding to each presented input. The memory cache interface presents a portion of a main memory address and a new value of a way signal to the memory cache until it finds a match between the output tag and the remainder of the main memory address. The memory cache interface allows set-associative caches to be constructed from simple memory blocks for use with devices in which the memory cache interface may be incorporated. The memory cache interface may be incorporated into such devices as data processors and microcontrollers.

Abstract: A method for use with a data coherency protocol has the steps of receiving a bus transaction in a data processor from a bus, receiving a first response from a memory location, .generating a first protocol signal, receiving a second response from the memory location, generating a second protocol signal and outputting either the first or second protocol signal responsive to the coherency protocol. The data processor operates at a clock frequency at least twice as fast as the bus. The data processor can query its memories at least twice and receive at least two responses during a single cycle of the bus clock. Therefore, the data processor can ignore busy responses from the memories that occur before the end of the single bus clock cycle.

Abstract: An interbus buffer (18) coordinates data transfers between two different sized buses. The first bus (processor bus) allows data to be ordered according to either a big endian protocol or a "munged" little endian mode. The second bus (local bus) allows data to be ordered according to either a big endian protocol or a true little endian mode but does not define a transaction size. The disclosed interbus buffer coordinates interbus data transfers in spite of the variety of different transaction sizes and operating modes.

Abstract: A store queue for use in a data processor (10) with a memory storage system has a first-in-first-out ("FIFO") queue (48) and control circuitry (52). The control circuitry maintains three pointers which index the entries in the FIFO queue: a dispatch pointer (D), a completion pointer (C), and an oldest miss pointer (OM). The control circuitry stores each stole instruction in the entry designated by the dispatch pointer and then increments the dispatch pointer. The control circuitry increments the completion pointer when the data processor indicates that the previously designated store instruction is the oldest instruction in the data processor: when the instruction is "completed." The control circuitry increments the oldest miss pointer after it presents the previously designated store instruction to the memory system.