Abstract: An exponent subtractor system (226) for a floating point adder (200) generates an exponent result (EXP.sub.-- low) and a rounded exponent result (EXP.sub.-- high) for an addition operation performed on two floating point numbers and generates overflow (Overflow.sub.-- low, Overflow.sub.-- high) and underflow flags (Underflow.sub.-- low, Underflow.sub.-- high) for the exponent result and the rounded exponent result before the completion of the updating of the exponent result in an exponent subtractor (52, 72).

Abstract: A mask-programmable read only memory bit cell (16) has a pair of conductive elements for each conductive layer in the integrated device but the last layer (30 and 34, 38 and 42, 46 and 50) and single conductive element in the last layer (54). The first and second elements in the first pair of elements receive a first and a second voltage supply (V.sub.DD and V.sub.GND), respectively. The single element outputs a voltage corresponding to the logic state stored by the bit cell. A plurality of pairs of conductive vias couple particular ones of the elements in each layer to particular ones of the elements in adjacent layers. The logic state stored by the bit cell may be reversed by reversing the connection of any one pair of elements and its associated vias. This makes the bit cell suitable for use in a processor version register.

Abstract: A capacitor for use in a memory cell (10). A transistor is formed overlying a substrate (10). The transistor has a first current electrode (16) and a second current electrode (18). The current electrodes (16 and 18) are separated by a channel region. A gate electrode (26) is formed overlying the channel region and is physically separated from the channel region by a gate dielectric layer (24). A plug region (32) is formed overlying and electrically connected to the first current electrode (16). An annular high-permittivity dielectric region (33) is formed overlying the transistor and is formed from a high-permittivity dielectric layer (36). A first capacitor electrode is formed via a conductive region (38"), and a second capacitor electrode is formed via a conductive region (38'). The memory cell (10) can be formed as a non-volatile memory cell or a DRAM cell depending upon various properties of the annular high-permittivity dielectric region (33).

Abstract: A method of transferring error correcting code has the steps of receiving a first data stream in a data processing system, generating a second data stream, and generating a correctable error signal. Initially, the data processing system outputs the first data stream. Later, the data processing system may select the second data stream to output responsive to a first predetermined transition of the correctable error signal. The second data stream and the correctable error signal are generated from the first data stream pursuant to an error correcting code protocol. The disclosed method permits high speed pipelined data processor operation.

Abstract: A result normalizer (58) for use with an adder (56) generates a mask in two stages that indicates the location of the leading one in the adder result. In the first stage, a leading zero anticipator (68) determines the position to within two digits. In the second stage, a count leading zero indicator (70) determines the position to a single digit. The mask is used to control the number of digits that each stage of a multiplexer array (66) shifts the adder result. The output of the multiplexer array thereby contains a leading one. The result normalizer may be advantageously used in high performance applications such as in a floating point execution unit in a data processor or in digital signal processing systems.

Abstract: An arbitration protocol comprises the steps of receiving a plurality of resource request signals (12), comparing the received plurality of resource request signals to a rotating pointer (14), and either granting the shared resource to the resource user specified by the rotating pointer (16) and incrementing the rotating pointer (18) or granting the shared resource to a resource user according to fixed priority protocol (20, 22, 24, 26 and 28). The rotating pointer specifies one of a plurality of resource users according to a predetermined order. The two steps of granting are responsive to the step of comparing.

Abstract: A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The first loading circuit couples a first logic state to the first node responsive to a first state of a control signal. The second loading circuit couples a second logic state to the first node responsive to a second state of the control signal. The buffer circuit electrically couples the first and second nodes. The first loading circuit, second loading circuit and buffer circuit are characterized by a first, a second and a third predetermined electrical impedance, respectively. The third loading circuit is coupled to the second node and is characterized by a fourth predetermined electrical impedance. The disclosed delay matching circuit propagates a clock signal input with a delay equal to the Clock-to-Q delay associated with a flip-flop constructed with similar circuit elements.

Abstract: A charge pump has a reference circuitry (18, 20, 22), a first parallel current path (16), at least one second parallel current path (16), a mirror circuit (46), a sourcing circuitry (60, 62) and a sinking circuitry (50, 54, 66, 68). The first and the at least one second parallel current path sink current from a first node responsive to a predetermined voltage generated by the reference circuitry. The at least one second current path also operates responsive to a control signal. The mirror circuit generates a second predetermined voltage responsive to the total current sunk from the first node. The sourcing circuitry and the sinking circuitry sourcing and sinking a current from the output node, respectively, responsive to the second predetermined voltage and to a control signal. The disclosed charge pump may be incorporated into a phase locked loop circuit where constant stability parameters are desired.

Abstract: A content addressable memory system has a plurality of associated circuit sets (12). Each circuit set has a tag memory element, a latching circuit and a data memory element. Each tag memory element stores a received tag in a first mode of operation and compares a received data tag to a stored data tag in a second mode of operation. In the second mode of operation, the tag memory element couples a first voltage supply terminal to an associated node in response to the comparison. Each latching circuit latches the voltage level present on its associated node during a first phase of a control signal. Each data memory element stores a data word and outputs the data word responsive to the latched voltage level of the associated latching circuit. The latching circuit continues to latch the voltage level and the data memory element continues to output its data word for an entire clock cycle.

Abstract: In accordance with the present invention, a resource allocation array has at least one resource input line (Aj), at least one request for resource input line (Ri) and at least one cell (12) coupled to the at least one resource input line and to the at least one request for resource line. The resource allocation array assigns one resource to one request for the resource. The one resource and the one request for the resource are both of a group of at least one resource and of a group of at least one request for the resource, respectively. The availability and unavailability of the resource is represented by a first and a second predetermined resource signal, respectively. The assertion and non assertion of the request for resource is represented by a third and a fourth predetermined request for resource signal, respectively. The at least one resource input line is associated with one of the at least one resource signals.

Abstract: A priority encoder (12) has a most significant bit circuitry (18), a first less significant bit circuitry (20) and a second less significant bit circuitry (22). The priority encoder detects a leading one within a plurality of data bits. Each data bit is associated with a different one of a plurality of input signals. The most significant bit circuitry is coupled to a first one of the input signals and generates a first output signal and a parallel blocking signal. Both of the first output signal and the parallel blocking signal are representative in a first logic state of a leading one associated with the first signal. The first less significant bit cell is coupled to a second one of the input signals and to the parallel blocking signal. The first less significant bit cell generates a second output signal and a less significant carry signal. Both the second output signal and the less significant carry signal are representative in a first logic state of a leading one associated with the second input signal.

Abstract: A latching sense amplifier (10) has sensing circuitry (12 and 14), latching circuitry (16) and switching circuitry (18). The sense amplifier operates between a first and a second voltage supply level and receives two input voltage levels. In a first mode, the sensing circuitry (12 and 14) generates two AC symmetric outputs representative of the voltage differential between the two input voltages. In a second mode, the latching circuitry (16) receives the two AC symmetric outputs and generates a second pair of outputs. The second pair of outputs is also representative of the voltage differential between the two input voltages. The voltage differential between the second pair of outputs is generally equal to the voltage differential between the first and second voltage supply levels. The switching circuitry (18) configures the sensing circuitry (12 and 14) to operate in conjunction with the latching circuitry (16) to form a cross coupled latch in the second mode.

Abstract: A precharge device (28) has a first (30) and a second node (32), a transistor tree (29), a screening transistor (Q20) and clocking circuitry (Q17, Q18, Q19). The transistor tree (29) couples the first (30) and the second (32) node and is operable to electrically short-circuit the nodes according to input signals (A.sub.1, A.sub.2, A.sub.3). The screening transistor (Q20) has a first and a second [source-drain region] current electrode and a [gate] control electrode. The first [source-drain region] current electrode is coupled to a third node (34), the second [source-drain region] current electrode is coupled to the second node (32) and the [gate] control electrode is coupled to the first node (30). The clocking circuitry alternately precharges the first (30) and third nodes (34) to a first known voltage level and evaluates the voltage on the first node (30) to output a logic level.