Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal.

Abstract: A thyristor power control circuit reduces EMI and maintains a holding current in the thyristor to prevent flickering at a load. The power control circuit includes a thyristor configured to receive an input AC voltage, and responsive to a gate pulse generates a modified AC voltage. A rectifier receives the modified AC voltage and generates a rectified DC voltage. A power converter coupled to the rectifier receives the rectified DC voltage and generates a controlled output current. A damping circuit coupled to an output terminal of the rectifier includes a damping resistor for maintaining the holding current in the thyristor during an ON period of the thyristor. The damping circuit includes a first capacitor coupled in series to the damping resistor and a diode coupled in parallel to the damping resistor. The diode enables the first capacitor to discharge without causing power loss at the damping resistor.

Abstract: A mobile device includes a communications protocol stack including a MAC layer and TCP layer separated by an IP layer. A cross-layer coordination module parallel to the communications protocol stack is coupled to both the MAC layer and TCP layer. The MAC layer generates a message sent to the cross-layer coordination module indicating that the mobile device is about to engage in a communications handover from a first base station to a second base station. The cross-layer coordination module passes handover information to the TCP layer so as to inform the TCP layer of the communications handover. If the mobile device is operating as a TCP sender, the TCP layer freezes its connection and state during the communications handover. If the mobile device is operating as a TCP receiver, the TCP layer sends a TCP ACK message to a TCP sender having an advertised window size set to a zero value so as to cause the TCP sender to freeze a connection and state during communications handover.

Abstract: A network-on-chip interconnects an array of integrated circuit resources. The network-on-chip includes at least one vertical communications ring per column of the array and at least one horizontal communications ring per row of the array. A network interface is associated with each resource of the array and operates to interface the communications rings with each other and the resource with the communications rings. A ring hop is provided at each network interface and for each communications ring thereat. Each ring hop functions as an add/drop multiplexer with respect to inserting packets onto the associated communications ring and extracting packets from the associated communications ring. Packets are communicated over the vertical/horizontal rings using a logical transport channel that flows in a cyclic manner through the communications ring without interruption.

Abstract: Clean and reliable channel sensing during dynamic frequency hopping over a plurality of overlapping wireless regional area network (WRAN) cells is conducted using a minimum number of channels. By coordinating a phase-shift of the operation periods of each WRAN cell over a minimum number of working channels, interruption-free communication and data transmission for each of the WRAN cells as well as interference-free channel sensing can be achieved.

Abstract: Collisions between tunneled direct link setup (“TDLS”) requests are resolved by associating each request with a priority value. Upon issuing a TDLS request the encapsulated frame is associated with a priority value. When a station, which is waiting for a response from a recently issued TDLS request, receives a TDLS request from another station, a collision occurs. The collision is resolved by comparing the priority value associated with the TDLS request initiated by the station and the TDLS request received. The TDLS request with the higher priority value is pursued while the TDLS request with the lower priority value is ignored. The priority value can be based on the sending station's MAC address or other value which can differentiate the TDLS requests.

Abstract: The quality of music output from audio systems is improved by simulating the effect of low frequency signals in the human ear. This thus allows listeners to perceive the lower frequency signals, even though the speakers may be incapable of providing such low frequency outputs. A method is provided for processing enhancing bass effect in audio signals. The method also results in the bass enhancement being computationally less intensive. The bass effect enhancement techniques are based on the response of sine and cosine transfer functions and on the directional independence of low frequency components. The human ear is unable to resolve directions from low frequency components. The bass effect enhancement technique alternatively is based on response of an exponential transfer function.

Abstract: A ball grid array (BGA) package includes a substrate layer having first and second sides. A semiconductor chip is attached to the first side of the substrate layer by a dielectric adhesive layer. A plurality of solder balls are attached to the second side of the substrate layer. The solder balls may be set out by rows and columns. A plurality of wires electrically connect the semiconductor chip to the solder balls. A layer of encapsulating compound is deposited over the semiconductor chip. A step cavity of a selected depth and shape is formed in the layer of encapsulating compound at or near the edge or periphery of the layer of encapsulating compound. The step cavity is separated from the solder balls by the substrate layer but spans over a plurality of selected solder balls.

Abstract: A method is provided for growth of carbon nanotube (CNT) synthesis at a low temperature. The method includes preparing a catalyst by placing the catalyst between two metal layers of high chemical potential on a substrate, depositing such placed catalyst on a surface of a wafer, and reactivating the catalyst in a high vacuum at a room temperature in a catalyst preparation chamber to prevent a deactivation of the catalyst. The method also includes growing carbon nanotubes on the substrate in the high vacuum in a CNT growth chamber after preparing the catalyst.

Abstract: In a process for enhancing contrast of an image having pixels in different brightness intensities, a histogram in discrete bins is generated. Each bin represents a pixel population of at least one pixel brightness intensity. A peak and a peak region of the histogram is then identified, wherein the peak region is a range of discrete bins around the peak. An average pixel population within the peak region is computed, and the pixel populations of the discrete bins within the peak region that exceeds the average pixel population are distributed. A transfer curve for mapping onto the image is then generated. The process can be used in an image processor for enhancing contrast of an image having pixel. Still further, a display having a receiver and a screen can include the foregoing image processor.

Abstract: A method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories.

Abstract: The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.

Abstract: An apparatus and method are disclosed for providing a power switch array with adjustable current rating power switches. A plurality of current rating power switches is provided that connects a power supply unit to a plurality of device ports. A power switch array controller is provided that adjusts an adjustable current rating in each of the plurality of adjustable current rating power switches. Each of the plurality of adjustable current rating power switches is adjustable to a selected number of current values. The power switch array controller dynamically adjusts the current ratings in the adjustable current power switches as required by the current requirements of the device ports.

Abstract: A tunable, linear operational transconductance amplifier includes a differential voltage to current conversion unit adapted to generate first and second output signals at respective first and second output nodes responsive to first and second differential input signals. A first current amplification unit is adapted to generate a third output signal responsive to the first output signal and first and second control signals. A second current amplification unit is adapted to generate a fourth output signal responsive to the second output signal and the first and second control signals.

Abstract: An embedded MEMS semiconductor substrate is set forth and can be a starting material for subsequent semiconductor device processing. A MEMS device is formed in a semiconductor substrate, including at least one MEMS electrode and a buried silicon dioxide sacrificial layer has been applied for releasing the MEMS. A planarizing layer is applied over the substrate, MEMS device and MEMS electrode. A polysilicon protection layer is applied over the planarizing layer. A silicon nitride capping layer is applied over the polysilicon protection layer. A polsilicon seed layer is applied over the polysilicon nitride capping layer. The MEMS device is released by removing at least a portion of the buried silicon dioxide sacrificial layer and an epitaxial layer is grown over the polysilicon seed layer to be used for subsequent semiconductor wafer processing.

Abstract: A filtering module filters out high frequency signals, primarily noise, from an input data stream. The filtering module includes an input module, a phase detecting module, and a threshold module. The input module performs either a charging or a discharging across a capacitor on a basis of an RC time constant. The phase detecting module is coupled to the input module to keep identical phase at a first node and an output node. The threshold module is coupled to the phase detecting module for providing an output signal based on a threshold voltage and the charging or the discharging across the capacitor.

Abstract: A circuit for glitchless switching between asynchronous clocks includes a select circuit and enable circuits. The select circuit receives a selection signal for selecting one of the clock input signals and to generate enabling signals for activating the corresponding enable circuits on the basis of the current output signal. The feedback logic in the circuit ensures that at any given instance only one of the clock input signals is outputted so as to avoid the formation of glitches. The circuit can be applied to switches between any number of asynchronous clocks.

Abstract: A smart card device includes a card body; and a plurality of card contacts carried by the card body. A smart card chip circuit includes a processor carried by the card body and operably connected to the contacts. At least one memory stores a set of instructions relating to initiating and completing smart card transactions between the smart card device and a smart card host. A biometric circuit is carried by the card body and operable with the processor and used for verifying identity of a user for subsequent smart card device usage. Power is received through a first contact for powering a power circuit for the smart card and a biometric subsystem power circuit receives power through a second contact.

Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is connected as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

Abstract: In a method for driving electronic devices connected to a vehicle trailer tow connector a trailer electronic device control signal is receiving from a vehicle data communication network. In response to the received control signal, a solid state power control device is switched to connect electrical power to a selected pin of the trailer tow connector. The trailer electronic device control signal may be received from a wiring harness connector connected to a vehicle data communication network. A vehicle trailer tow connector module includes a module housing. A vehicle wiring connector and a trailer wiring connector are coupled to the module housing. A power control circuit is connected to a selected pin in the trailer wiring connector. A controller circuit is coupled to the vehicle wiring connector for receiving communication data from a vehicle data bus, and coupled by control lines to the power control circuit.