Abstract: A phase-acquisition (PA) loop for a read channel comprises an accumulator, a comparator, and a filter. The accumulator holds an acquired phase-correction value corresponding to a difference between a phase of a sample clock and a phase of data carried by a read signal, and provides the acquired phase-correction value to a circuit that modifies the read signal to compensate for the phase difference. The comparator receives a reference phase-correction value that also corresponds to the difference between the phases of the sample clock and the data, and generates an error signal that is related to a difference between the reference and acquired phase-correction values. And the filter causes the acquired phase-correction value to have a predetermined relationship to the reference phase-correction value.

Abstract: A method includes extracting at least one object file from a library of object files. The method also includes identifying an interprocedural optimization associated with a plurality of object files. The plurality of object files includes the at least one extracted object file. The method further includes invoking recompilation of at least one of the plurality of object files to implement the identified interprocedural optimization. In addition, the method includes generating at least one executable file using the at least one recompiled object file. The plurality of object files could include interprocedural summary information generated by a compiler during a compilation of at least one source file and a compiler internal representation associated with the compiler during the compilation. The interprocedural optimization could be identified using the interprocedural summary information, and the at least one recompiled object file could be generated using the compiler internal representation.

Abstract: A gain controller for a gain loop of a read channel includes a comparator circuit, an accumulator circuit, and a function circuit. The comparator circuit determines an error between an actual sample of a read signal and a corresponding ideal sample of the read signal, and the accumulator circuit holds a gain-correction value and adjusts the gain-correction value in response to the error. The function circuit generates a gain-correction signal by performing a predetermined mathematical operation involving the gain-correction value, and provides the gain-correction signal to a variable-gain amplifier that is operable to amplify actual samples of the read signal. Because such a gain controller allows one to locate the variable-gain amplifier (VGA) after the analog-to-digital converter (ADC) in a read channel, the gain controller may significantly reduce the latency of the gain-acquisition (GA) loop or the gain-tracking (GT) loop of the read channel.

Abstract: Counter-clockwise and clockwise quadrant transitions are detected and accumulated with respect to a received complex signal over a certain time period. These transitions may then be compared in order to obtain information indicative of both a magnitude and phase of a carrier frequency error for the received signal. Additionally, zero-crossings of the received complex signal over the same certain time period are detected and accumulated. The accumulated crossings provide information indicative of frequency offset magnitude. The determined magnitude and phase of the frequency error may then be used to adjust a local oscillator frequency to provide for improved receiver performance.

Abstract: First and second integer transform matrices can be used to approximate the discrete cosine transform. An input matrix of data is multiplied by a first transform matrix of integers to produce an intermediate matrix of data. The intermediate matrix is multiplied by a second transform matrix of integers to produce a transform result matrix of data. The multiplications by the first and second transform matrices can be pipelined to increase throughput. A plurality of transform data paths can also be provided in parallel to increase throughput.

Abstract: There is disclosed a data processor that executes variable latency load operations using bypass circuitry that allows load word operations to avoid stalls caused by shifting circuitry.

Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.

Abstract: A blind carrier frequency offset estimator is based on a single-OFDM-symbol training sequence in multi-user OFDMA uplink. Through multiple access interference modeling and analysis, a virtual user is employed that occupies the all null sub-carriers. By minimizing the energy leakage on the virtual user in term of tentative frequency offsets, the estimator can approach the real frequency offset. The estimator performs only on frequency-domain, simplifies interference calculations, and lowers the rank of the matrix. An iterative computation method is used to approach the real frequency offset.

Abstract: A circuit includes an OPAMP-less bandgap voltage generating core circuit connected between a regulated voltage and a ground reference to generate an output bandgap voltage. A preregulator circuit generates the regulated voltage from an unregulated supply voltage. The preregulator circuit includes a negative feedback loop operable to stabilize the regulated voltage and a current source operable to source current for the regulated voltage, the current source mirroring a PTAT current of the OPAMP-less bandgap voltage generating core circuit. The core circuit further includes a negative feedback loop and a positive feedback loop, the negative and positive feedback loops functioning to equalize two internal voltages within the core.

Abstract: In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the victim line. The induced voltage pulse is counteracted by coupling the victim line to a counteracting voltage source. After a predetermined delay period, the coupling of the counteracting voltage source is removed from the victim line. The voltage change on the aggressor line my be sensed from a node connected to either the aggressor line or the victim line. A rising induced pulse is counteracted by coupling the victim line to a more negative voltage source, and a falling induced pulse is counteracted by coupling the victim line to a more positive voltage source.

Abstract: An H-bridge driver for a disk drive system includes first and second high side switched legs and first and second low side switched legs. An inductor head for writing data to and reading data from a magnetic media is connected to form a center of the H-bridge. The system includes a voltage regulator circuit that generates a common mode regulated voltage. First and second high side logic circuits, which selectively control operation of the first and second high side switched legs, are coupled between a high reference voltage and the common mode regulated voltage. First and second low side logic circuits, which control the first and second low side switched legs, are coupled between the common mode regulated voltage and ground.

Abstract: An MPEG-1 layer 3 audio encoder, including a scalefactor generator for determining first scalefactors for encoding a block of audio data if a temporal masking transient is not detected in said block of audio data; and for selecting the maximum of said scalefactors for encoding said block of audio data if a temporal masking transient is detected in said block of audio data to enable greater compression of said audio data. Increases in quantization error, due to use of the maximum scalefactor are pre-masked or post-masked by the temporal masking transient. In cases where the last portion of a block includes a temporal masking transient that masks the preceding portions of the block, the maximum scalefactor is only used to encode the block if the resulting increase in quantization error is less than 30% of the quantization error for the block.

Abstract: A digital-to-analog converter, in response to a digital signal, selectively taps a resistor string to generate an analog output and selectively shunts around resistors in the string to voltage shift the analog output. If two supply voltage sets are present, two strings are provided. A mutually exclusively selection of outputs is made to select a source of the analog output. An integrated circuit temperature sensor uses the converter and includes a sensing circuit that determines exposure to one of a relatively low or high temperature. A measured voltage across the base-emitter of a bipolar transistor is selected in low temperature exposure and compared against a first reference for a too cold temperature condition. Alternatively, a measured delta voltage across the base-emitter is selected in high temperature exposure and compared against a second reference voltage for a too hot temperature condition. Through the comparisons, a temperature exposure detection is made.

Abstract: A floating point unit, a central processing unit, and a method are provided for adjusting the exponent of a floating point number. During an addition or subtraction of two floating point numbers, the significand of the floating point result is rounded, and the exponent of the result may be adjusted due to normalization or renormalization. The exponent adjustment due to renormalization or the exponent adjustment due to normalization and renormalization is combined with the significand rounding operation.

Abstract: An integrated circuit burn-in test system includes an integrated circuit and a tester. The integrated circuit includes operating circuitry, a heater for heating the operating circuitry, and burn-in test circuitry for testing the operating circuitry while being heated. A package surrounds the operating circuitry, the heater and the burn-in test circuitry. The burn-in test circuitry causes the operating circuitry to operate and generate data related thereto. The tester receives data from the burn-in test circuitry. The heater may be configured within the package to heat at least one predetermined portion of the operating circuitry.

Abstract: A cryptographic system comprising: 1) a first Montgomery-based cryptographic engine that receives a first operand and a second operand and generates a first result and 2) a second Montgomery-based cryptographic engine that receives a first reduced operand derived from the first operand and a second reduced operand derived from the second operand and generates a second result. The second Montgomery-based cryptographic engine operates in parallel with the first Montgomery-base cryptographic engine. The cryptographic system further comprises a comparator for comparing the second result to a first reduced result derived from the first result and generating an error flag if the second result and the first reduced result are different.

Abstract: For use in a pipeline network search engine of a router, a path compression optimization system and method is disclosed for eliminating single entry trie tables. The system embeds in a parent trie table (1) path compression patterns that comprise common prefix bits of a data packet and (2) skip counts that indicate the length of the path compression patterns. The network search engine utilizes the path compression patterns and the skip counts to eliminate single entry trie tables from a data structure. Each path compression pattern is processed one stride at a time in subsequent pipeline stages of the network search engine. The elimination of unnecessary single entry trie tables reduces memory space, power consumption, and the number of memory accesses that are necessary to traverse the data structure.

Abstract: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set.

Abstract: A key switch matrix circuit includes key switches arranged in rows and columns, each row having a scan line, each column having a sense line. Each key switch is operable to couple a scan line to a sense line. A scan signal delivery circuit supplies scan signals to the scan lines, the scan signals delivering a scan pulse to each row of the key switch matrix circuit in turn. A key switch detection circuit outputs a first signal if a key switch is operated and a scan pulse detection circuit outputs a second signal if a scan pulse is coupled to a sense line. The scan signal delivery circuit begins supplying scan signals in response to the first signal and stops supplying scan signals in response to the second signal. In one embodiment, a processor reads the sense lines in response to the second signal.

Abstract: The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit device in the test mode, a clock signal (either an external clock signal or an associated internal clock signal) is internally clocked. As the clock signal goes to a low logic state upon power-up of the device, a master latch (flip-flop) flip-flop element of the integrated circuit device is loaded with data and is allowed to conduct; a slave latch (flip-flop) flip-flop element of the integrated circuit device does not conduct. As the clock signal goes to a high logic state, the data in the master latch is latched. Also upon the high logic state of the clock, the slave latch element is loaded with data and is allowed to conduct.