Abstract: A zero current detector for a DC-DC converter includes a first transistor having a drain, a gate, and a source for sensing the voltage of a first terminal of a power transistor; a second transistor having a drain, a gate, and a source for sensing the voltage of a second terminal of a power transistor; and a third transistor having a coupled gate and drain for receiving a reference current that is coupled to the gates of the first and second transistors and a source coupled to the source of the first transistor, wherein an output signal is provided by the drains of the first and second transistors. A load is coupled to the drains of the first and second transistors. The zero current detector also includes a fourth transistor having a current path coupled between the source of the second transistor and the second terminal of the power transistor and a gate for receiving a control signal.

Abstract: A communication signal carrier on a communication channel in a digital cable receiver can be characterized as analog without exhaustively attempting to determine a symbol rate or modulation scheme of a digital carrier. The signal level in the channel is observed at different channel bandwidths, and these observations are used to differentiate between analog and digital carriers.

Abstract: A substrate clamp ring has an edge exclusion lip with a variable bottom surface. At least a portion of that bottom surface has a height above the substrate contact level selected to minimize accumulation over time of deposited aluminum-copper alloy across lower portions of the bottom surface, and to allow the aluminum-copper alloy to be deposited to a thickness of at least 2 microns on each of a predetermined number of substrates without bridging. The height of the bottom surface at an innermost edge of the lip is preferably about 17 mils, while a height of the bottom surface over the substrate edge is preferably about 8.5 mils.

Abstract: A series of hardware pipeline units each processing a stride during prefix search operations on a multi-bit trie includes, within at least one pipeline unit other than the last pipeline unit, a mechanism for retiring search results from the respective pipeline unit rather than passing the search results through the remaining pipeline units. Early retirement may be triggered by either the absence of subsequent strides to be processed or completion (a miss or end node match) of the search, together with an absence of active search operations in subsequent pipeline units. The early retirement mechanism may be included in those pipeline units corresponding to a last stride for a maximum prefix length shorter than the pipeline (e.g., 20 or 32 bits rather than 64 bits), in pipeline units selected on some other basis, or in every pipeline unit. Worst-case and/or average latency for prefix search operations is reduced.

Abstract: A resonant power converter for ultra-efficient radio frequency transmission and associated methods. In one exemplary embodiment, the invention is digitally actuated and uses a combination of a noise-shaped encoder, a charging switch, and a high-Q resonator coupled to an output load, typically an antenna or transmission line. Energy is built up in the electric and magnetic fields of the resonator, which, in turn, delivers power to the load with very little wasted energy in the process. No active power amplifier is required. The apparatus can be used in literally any RF signal application (wireless or otherwise), including for example cellular handsets, local- or wide-area network transmitters, or even radio base-stations.

Abstract: A transmission gate includes first and second MOS transistors of opposite conductivity type coupled in parallel with each other. Each transistor includes a body connection that is separately biased by corresponding first and second biasing circuits. The first biasing circuit generates a first bias voltage having a voltage level that is generated as a function of the signal at the first node and a first (for example, positive) reference voltage. The second biasing circuit generates a second bias voltage having a voltage level that is generated as a function of the signal at the first node and a second (for examples ground) reference voltage.

Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.

Abstract: A level shifter for integrated circuits includes input stage transistors, reference stage transistors, a cascode stage coupled to the input stage and the reference stage transistors and a pair of comparators. The cascode stage generates a first cascode output and a second cascode output. The input stage transistors selectively conduct a low reference voltage as the first cascode output based on a pair of inputs provided to the input stage transistors. The reference stage transistors selectively conduct a high reference voltage as the second cascode output based on a first comparator output and a second comparator output. The pair of comparators generate the first and the second comparator outputs based on the first and the second cascode outputs.

Abstract: An integrated circuit and method for monitoring and controlling power and for identifying an open circuit state at an output port is disclosed. A circuit is implemented to determine whether an open circuit state exists based on a comparison of data received from the output port and attached loads. The data received from the output port and attached loads is compared to a minimum open circuit current value of the output port, wherein the minimum open circuit current value is based on the hardware characteristics of the output port and attached loads. A possible open circuit state at the output port is reported based on the comparison.

Abstract: A disk-controller (110) that is within a disk memory system (100) initiates the auto-transfer of host-requested-data from cache memory (120) without the intervention of a microprocessor (130) that is within the disk memory system. The system performs auto-transfer, without the intervention of the microprocessor, even when the first block of host-requested-data (301) is not within cache memory (311). The system includes disk-controller circuitry (11) that determines when at least a portion of the host-requested-data is somewhere within cache memory.

Abstract: A system and method is disclosed for efficiently executing single program multiple data (SPMD) programs in a microprocessor. A micro single instruction multiple data (SIMD) unit is located within the microprocessor. A job buffer that is coupled to the micro SIMD unit dynamically allocates tasks to the micro SIMD unit. The SPMD programs each comprise a plurality of input data streams having moderate diversification of control flows. The system executes each SPMD program once for each input data stream of the plurality of input data streams.

Abstract: A system of detecting biometric and non-biometric, standard smart card devices includes a smart card host and smart card device reader, which is operable for receiving an Answer to Reset signal and determining whether the smart card device comprises a biometric or non-biometric, standard smart card device. If a biometric smart card device is detected, the smart card reader is operable for applying power used for standard smart card device operation to a first contact and applying power used by a biometric circuit to a second contact, and if a non-biometric, standard smart card device is detected, applying power only to the first contact.

Abstract: An integrated circuit device and method for classifying electrical devices is disclosed. A reference current response of a plurality of electrical devices is determined and stored in a memory. Real-time current response of a specific electrical device is measured and stored in the memory. A processor compared the measured real-time current response of the specific electrical device to the reference current responses of the plurality of electrical devices. A classification of the electrical device is then made based on the comparison.

Abstract: An integrated circuit for a smart card in accordance with an exemplary embodiment includes a transceiver and a processor for communicating with a host device via the transceiver. More particularly, the processor provides at least one default descriptor to the host device, and cooperates with the host device to perform an enumeration based upon the at least one default descriptor. Moreover, the processor also detects a system event and, responsive to the system event, provides at least one alternate descriptor to the host device and cooperates with the host device to perform a new enumeration based thereon.

Abstract: To optimize the performance of DSL modems in the same cable bundle, the size and position of the group of subcarriers used for transmission is intelligently selected when the bit rate necessary for making the transmission is less than the total available bandwidth provided by all subcarriers. By intelligently selecting a minimum number of subcarriers for Digital Multi-tone (DMT) signal transmission, a reduction in line driver power consumption is effectuated. Additionally, by intelligently selecting the position of the groups of subcarriers within the total available subcarriers, near-end crosstalk (NEXT) noise within the cable bundle may be minimized.

Abstract: A Dynamic Frequency Hopping Community (DFH Community) is formed from a plurality of Wireless Regional Area Network (WRAN) cells wherein each of the plurality of WRAN cells within the DFH Community is a one-hop neighbor of the leader cell. The leader cell sets and distributes a hopping pattern for use among the WRAN cells based on, in part, the number of usable channels and whether a WRAN cell is shared by two groups in the DFH Community.

Abstract: A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction loop that iteratively processes a message that is encoded prior to transmittal over a communication channel. The error correction loop generates, such as with a Reed-Solomon decoder, an error location polynomial in each iterative process. A stopping mechanism in the decoder allows an additional iteration of the message decoding based on the error location polynomial, such as by obtaining the degree of the error location polynomial and comparing it to a threshold. In one example, the threshold is the maximum number of symbol errors correctable by the Reed-Solomon code embodied in the decoder. The stopping mechanism allows additional iterations when the stopping criterion (or polynomial degree) is greater than the maximum number of symbol errors correctable by the Reed-Solomon code.

Abstract: A method for providing cascaded trie-based network packet search engines is provided. A search command is received at one of the network packet search engines. The search command comprises a specific search key. A determination of a longest prefix match based on the specific search key is made at the network packet search engine. A determination is made at the network packet search engine regarding whether the longest prefix match comprises an overall longest prefix match among the cascaded network packet search engines such that any of the cascaded network packet search engines may comprise the overall longest matching prefix independently of position relative to the other cascaded network packet search engines.

Abstract: Disk drive spindle jitter is comprised of electrical noise, error due to pair pole asymmetry, and random disk speed variances. Error caused by pair pole asymmetry can be identified and compensated for by detecting over a single rotation of a rotor a plurality of zero cross signals. These signals can be statistically analyzed over a period of a plurality of revolutions of the rotor so as to identify the systematic error caused by pair poles. Once identified, this pair pole error can be used to modify zero cross signals and/or modify commutation signal driving the disk so as to arrive at a more accurate determination of disk speed and to precisely control the speed of the disk.

Abstract: A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.