Abstract: A system and method for adaptive rate control in audio processing is provided. The process could include receiving uncompressed audio data from an input and generating MDCT spectrum for each frame of the uncompressed audio data using a filterbank. The process could also include estimating masking thresholds for current frame to be encoded based on the MDCT spectrum. The masking thresholds reflect a bit budget for the current frame. The process could also include performing quantization of the current frame based on the masking thresholds. After the quantization of the current frame, the bit budget for next frame is updated for estimating the masking thresholds of the next frame. The process could also include encoding the quantized audio data.

Abstract: A method includes receiving a sequence of frames containing audio information and determining that a frame is missing in the sequence of frames. The method also includes comparing the frame that precedes the missing frame to the received frames to identify a selected frame. The method further includes identifying a replacement frame comprising the frame that follows the selected frame. In addition, the method includes inserting the replacement frame into the sequence of frames in place of the missing frame.

Abstract: This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and more particularly to a method of addressing inter-systems (cells) coexistence and spectrum sharing. The described method of spectrum sharing, called On-Demand Spectrum Contention, integrates Dynamic Frequency Selection and Transmission Power Control with iterative on-demand spectrum contentions and provides fairness, adaptability, and efficiency of spectrum access for dynamic spectrum access systems using active inter-system coordination.

Abstract: A method of gain control by amplifying an input signal with a variable gain amplifier to generate an output signal where the gain of the variable gain amplifier is selected based upon a control signal presented at a control input of the variable gain amplifier. When the output signal is larger than the upper boundary, incrementally changing the magnitude of the control signal so as to reduce the gain of the variable gain amplifier in a step-wise linear fashion. When the output signal is smaller than the lower boundary, incrementally changing the magnitude of the control signal so as to increase the gain of the variable gain amplifier in a step-wise linear fashion.

Abstract: A row driver circuit receives a first supply voltage and a second supply voltage. The circuit provides the first supply voltage on an output responsive to the first supply voltage being greater than a threshold value. The circuit generates a boosted voltage that is greater than the first supply voltage and provides that boosted voltage on the output responsive to the first supply voltage being less than the threshold value.

Abstract: An apparatus such as a Device Wire Adapter (DWA) with improved buffer management and packaging of Wireless Universal Serial Bus (WUSB) isochronous packets for transmission to a host. The apparatus includes an isochronous IN endpoint that receives data segments from a device function. Memory is associated with the endpoint and includes an endpoint buffer configured in a loop and a plurality of registers. The apparatus includes an endpoint controller that stores the received data segments sequentially in the loop buffer, assigns a set of the registers to each of the stored data segments, and stores additional packet information in the registers for each of the data segments rather than in the endpoint buffer. The additional packet information includes presentation time for the stored data segment derived from a sample time of a last segment in the buffer and a time interval between two consecutive data segments in the buffer.

Abstract: A memory comprises at least one array of memory elements, a partition of the at least one array into a plurality of sub-arrays of the memory elements, and an array configuration circuit for selectively putting the at least one array in one of two operating configurations. In a first operating configuration, the memory elements of the at least one array are coupled one to another to form a monodimensional sequentially-accessible memory, while in a second operating configuration the memory elements in each sub-array are coupled to one another so as to form an independent monodimensional sequentially-accessible memory block, a data content of any memory element of the sub-array being rotatable by shifts through the memory elements of the sub-array. A sub-array selector, responsive to a first memory address, selects one among the at least two sub-arrays according to the first memory address, and enables access to the selected sub-array.

Abstract: The present invention provides a system and an apparatus for a digital audio/video decoder comprising a file reader capable of obtaining an encoded audio/video data stream from a data source, a navigator that instructs the file reader to obtain the encoded audio/video data stream, a splitter that separates the encoded audio/video data stream obtained by the file reader into one or more component data streams, and a reprogrammable proxy filter that decodes and converts the one or more component data streams into three or more renderable signals including at least one renderable audio signal and at least two renderable video signals.

Abstract: A multi-chip system in which at least one of the chips includes a performance parameter encoded thereon. After system assembly, the performance parameter can be obtained by a companion chip and used to automatically or semi-automatically fine tune the companion chip to the specific parameters of the at least one chip.

Abstract: An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the real time data. Further, each register may include a master latch for initially storing the real time data bit, a slave latch for subsequently storing the real time data bit, and a user latch for storing the real time data bit from the slave latch. The RTC circuit may further include a controller for causing at least some of the registers to increment based upon the clock reference signal. Additionally, the electronic timer may also advantageously include a tamper circuit for receiving a tamper event signal and causing each of the user latches to hold a time stamp therein.

Abstract: A processor executes one or more prefetch threads and one or more main computing threads. Each prefetch thread executes instructions ahead of a main computing thread to retrieve data for the main computing thread, such as data that the main computing thread may use in the immediate future. Data is retrieved for the prefetch thread and stored in a memory, such as data fetched from an external memory and stored in a buffer. A prefetch controller determines whether the memory is full. If the memory is full, a cache controller stalls at least one prefetch thread. The stall may continue until at least some of the data is transferred from the memory to a cache for use by at least one main computing thread. The stalled prefetch thread or threads are then reactivated.

Abstract: A data-storage disk includes a disk sector for storing data and a servo wedge located at the beginning of the sector. The servo wedge indentifies the sector in conjunction with both an initial positioning of a read-write head and a data read or write operation. By using a servo wedge to provide both an initial head position on disk spin up and a head position during a read or write operation, one can increase a disk's data-storage capacity by reducing the number of, or altogether eliminating, spin-up wedges.

Abstract: A system for supporting software pipelining using a shifting register queue is provided. The system includes a register file that comprises a plurality of registers. The register file is operable to receive a shift mask signal and a shift signal and to identify a shifting register queue within the register file based on the shift mask signal. The shifting register queue comprises a plurality of queue registers. The register file is further operable to shift the contents of the queue registers based on the shift signal.

Abstract: A detector recovers servo data from a servo signal generated by a read-write head, and determines the head-connection polarity from the recovered servo data. Such a detector allows a servo circuit to compensate for a reversed-connected read-write head, and thus allows a manufacturer to forego time-consuming and costly testing to determine whether the head is correctly connected to the servo circuit.

Abstract: A battery monitor circuit. The circuit includes a control module, a resistive load having a resistive value between a first and a second terminals and a part of that resistive value between the first and an intermediate terminals, a switch configured to couple the full load between circuit input and a common potential in response a pulse signal, a first comparator having inputs separately coupled to a voltage reference and the intermediate terminal, a second comparator having inputs separately coupled to the voltage reference and an input potential, a latch, a detection module having input coupled to second comparator output, and an alarm module. The latch is configured to latch a value at output of first comparator to another input of the detection module in response to the pulse signal; if input potential is less than a preselected magnitude, detection module output is configured to activate the alarm module.

Abstract: To improve the performance of DSL modems, a DSL duplexing ratio for a new communication is selected according to the communications needs of an application. A required upstream and downstream bit rate for application communications is determined. From the ratio of these bit rates, a desired duplexing ratio is calculated. The operation of the modem is then adapted to choose a duplexing ratio that approximates the desired duplexing ratio for the application. To optimize modem operation, the size and position of the upstream and downstream bandwidths used for transmission are intelligently selected when the bit rate necessary for making the transmission is less than the total available bandwidth provided by the chosen duplexing ratio. By intelligently selecting a minimum number of subcarriers for Digital Multi-tone (DMT) signal transmission, a reduction in line driver power consumption is effectuated.

Abstract: A threshold personalization circuit for a reset or supervisor chip includes personalization fuses, which shift a resistor divider to provide a variety of selectable voltage thresholds. The personalization fuses may provide hundreds of millivolts of adjustment. The threshold personalization circuit further includes trim fuses to fine tune the threshold to within a few millivolts of the target threshold voltage. The threshold personalization circuit includes a test mode to cycle through to a particular personalization trim, such that at prelaser testing the personalized value is found (the fuse blow for personalization is emulated) and then the trim fuse amount can be based on the actual final personalized voltage. This results in very accurate threshold voltages for all personalized values.

Abstract: The present disclosure provides a method for detecting flicker DC voltage offset. The method includes receiving an output signal of an image sensor, the output signal comprising a reference signal and an image signal, and generating a combined signal by combining the image signal with a peak flicker DC voltage signal during a first time period. The method also includes performing an auto zero function in an auto zeroing comparator during the first time period between the reference signal and the combined signal and comparing the reference signal and the image signal with the auto zeroing comparator during a second time period subsequent to the first time period. The method further include storing a first charge corresponding to the image signal during a second time period and storing a second charge corresponding to a current peak flicker DC voltage signal.

Abstract: An apparatus includes a display panel capable of displaying content. The apparatus also includes a light sensor having an integrated circuit and a photo-sensitive device. The photo-sensitive device is capable of measuring an amount of ambient light. The integrated circuit is capable of performing one or more functions associated with the display of the content on the display panel. The apparatus further includes a controller capable of adjusting one or more characteristics of the display panel based on the amount of ambient light measured by the light sensor. The integrated circuit and the photo-sensitive device may be formed on one side of a semiconductor wafer, and the photo-sensitive device may be exposed to the ambient light through an opening in an opposing side of the semiconductor wafer.

Abstract: An integrated control and power driving system moves a read/write head carrying arm over the surface of a disk. The integrated control and power driving system is applicable to a spindle motor, a mass storage disk drive and a voice-coil motor, for example, and includes a first chip and a second chip. The first chip integrates the output power stages driving the motors, and has an interface for outputting feedback signals representing functioning conditions of the voice-coil motor and of the spindle motor, and for receiving digital control signals of the output power stages. The second chip integrates logic drive and control circuitries of the power stages and an interface for receiving the feedback signals output by the first chip, and for transmitting to the first chip the digital control signals.