Abstract: A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M are greater than or equal to 2 and the size of the N by M array is selected such that each of the plurality of BGA substrates (12) maintains a planarity variation less than approximately 0.15 mm (approximately 6 mils). The printed wiring board (11) has a thickness (26) sufficient to minimize planarity variation and to allow a manufacturer to use automated assembly equipment without having to use support pallets or trays.

Abstract: An ESD protection device (20) comprises an N-type epitaxial collector (21), a first, lightly doped, deep base region (221) and second, highly doped, shallow base region (222) that extends a predetermined lateral dimension. The device responds to an ESD event by effecting vertical breakdown between the base regions and the N-type epitaxial collector. The ESD response is controlled by the predetermined lateral dimension, S, which, in one embodiment, may be is determined by a single masking step. Consequently, operation of the ESD protection device is rendered relatively insensitive to the tolerances of a fabrication process, and to variations between processes.

Abstract: An implant-free enhancement mode metal-oxide semiconductor field effect transistor (EMOSFET) is provided. The EMOSFET has a III-V compound semiconductor substrate and an epitaxial layer structure overlying the III-V compound semiconductor substrate. The epitaxial material layer has a channel layer and at least one doped layer. A gate oxide layer overlies the epitaxial layer structure. The EMOSFET further includes a metal gate electrode overlying the gate oxide layer and source and drain ohmic contacts overlying the epitaxial layer structure.

Abstract: Shielded electronic integrated circuit apparatus (5) includes a substrate (10), with an eletronic integrated circuit (15) formed thereon, and a dielectric region (12) positioned on the electronic integrated circuit. The dielectric region and the substrate are substantially surrounded by lower and upper magnetic material regions (26, 30), deposited using electrochemical deposition, and magnetic material layers on each side (32, 34). Each of the lower and upper magnetic material regions preferably include a glue layer (36, 40), a seed layer (28, 24), and an electrochemically deposited magnetic material layer (26, 30). Generally, the electrochemically deposited magnetic material layer can be conveniently deposited by electroplating.

Abstract: A first gate (120) and a second gate (122) are preferably PMOS and NMOS transistors, respectively, formed in an n-type well (104) and a p-type well (106). In a preferred embodiment first gate (120) includes a first metal layer (110) of titanium nitride on a gate dielectric (108), a second metal layer (114) of tantalum silicon nitride and a silicon containing layer (116) of polysilicon. Second gate (122) includes second metal layer (114) of a tantalum silicon nitride layer on the gate dielectric (108) and a silicon containing layer (116) of polysilicon. First spacers (124) are formed adjacent the sidewalls of the gates to protect the metals from chemistries used to remove photoresist masks during implant steps. Since the chemistries used are selective to polysilicon, the spacers (124) need not protect the polysilicon capping layers, thereby increasing the process margin of the spacer etch process. The polysilicon cap also facilitates silicidation of the gates.

Abstract: A semiconductor nonvolatile memory cell (30) comprising a split-gate FET device having a charge-storage transistor (38) in series with a select transistor (39). A multilayered charge-storage gate dielectric (35) extends over at least a portion of the source (32) and a first portion (341) of the channel of the FET. A select gate dielectric (36), contiguous to the charge-storage gate dielectric, extends over at least a portion of the drain (33) and a second portion (342) of the channel. A monolithic gate conductor (37) overlies both the charge-storage gate dielectric and the select gate dielectric. In an embodiment, the charge-storage gate dielectric is an ONO stack that incorporates a thin-film nitride charge-storage layer (352). The select transistor operates to inhibit over-erasure of the NVM cell. The thin-film nitride charge-storage layer extends laterally over a substantial portion of the channel so as to enhance data retention by the cell.

Abstract: The invention relates to a method for measuring a required feature of a thin layer (4) used in a polishing process that is carried out by a polish head by producing a localized temperature rise on the surface of the layer (4) by focusing a short pump laser pulse (11) on the surface of the layer, as to generate a sound wave (13) that propagates into the layer; repeated measuring the surface reflection properties of the layer, by passing a probe laser pulse (21) and focusing it on the surface of the layer and by monitoring the portion of the probe laser pulse that is reflected (22) by the surface, as to detect a change in surface reflection properties caused by a boundary echo (32) that is a reflected part of the sound wave (13); measuring the elapsed time between the generation of the sound wave and the change in surface reflection properties; and calculating the required layer feature. Furthermore the invention relates to a measuring apparatus, which is able to perform the above-mentioned method.

Abstract: A semiconductor device (10) having two different gate dielectric thicknesses is formed using a single high-k dielectric layer, preferably a metal oxide. A thicker first gate dielectric (16) is formed in a region of the device for higher voltage requirements, e.g. an I/O region (24). A thinner second gate dielectric (20) is formed in a region of the device for lower voltage requirements, e.g. a core device region (22). First and second dielectrics are preferably silicon dioxide or oxynitride. A metal oxide (26) is deposited over both dielectrics, followed by deposition of a gate electrode material (28). By using a single metal oxide layer in forming the gate dielectric stack for each transistor, together with high quality silicon dioxide or oxynitride dielectric layers, problems associated with selective etching of the metal oxide may be avoided, as may problems associated with various interfaces between the metal oxide and damaged or treated surfaces.

Abstract: A dielectric layer comprises lanthanum, aluminum, nitrogen, and oxygen and is formed between two conductors or a conductor and substrate. In one embodiment, the dielectric layer is graded with among the lanthanum, nitrogen, or aluminum. An additional insulating layer may be formed between the conductor or substrate and the dielectric layer. The dielectric layer can be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.

Abstract: A semiconductor device (10) having a gate (15), a source (19), and a drain (20) with a gate bus (25) and first ground shield (24) patterned from a first metal layer and a second ground shield (31) patterned from a second metal layer. The first ground shield (24) and the second ground shield (31) lower the capacitance of device (10) making it suitable for high frequency applications and housing in a plastic package.

Abstract: A method for monitoring a polishing condition of a surface of a wafer in a polishing process is provided, the method comprising providing a wafer (16) to be polished, the wafer (16) having at least one optically distinguishable feature (20) below a transparent or translucent layer (22) to be polished; selecting one or more of the features (20) for monitoring; measuring an optical contrast profile (62; 72; 82; 92) across one or more of the selected features (20); determining the polishing condition of the surface of the wafer (16) on the basis of the measured contrast profile (62; 72; 82; 92); and repeating the measuring the optical contrast profile (62; 72; 82; 92) and determining the polishing condition until a predetermined polishing condition is reached. A method for polishing wafers by a CMP polishing tool and apparatus for monitoring a polishing condition of a surface of a wafer (16) is also provided.

Abstract: A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M are greater than or equal to 2 and the size of the N by M array is selected such that each of the plurality of BGA substrates (12) maintains a planarity variation less than approximately 0.15 mm (approximately 6 mils). The printed wiring board (11) has a thickness (26) sufficient to minimize planarity variation and to allow a manufacturer to use automated assembly equipment without having to use support pallets or trays.

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract: The present invention relates to a method of determining a thickness of at least one layer on at least one semiconductor wafer (12), comprising the steps of: projecting a first laser pulse (14) on a surface (16) of the at least one layer (10), thereby generating an acoustical wave due to heating of the surface of the at least one layer (10); after a propagation time of the acoustical wave, projecting a series of second laser pulses (18) on the surface (16) of the at least one layer (10); measuring reflected laser pulses (20) of the second laser pulses (18), thereby sensing the times of reflection property changes of the surface (16) of the at least one layer (10); and determining the thickness of the at least one layer (10) by analyzing the times of reflection property changes. The present invention further relates to a system for determining a thickness of a layer (10) on a semiconductor wafer (12).

Abstract: The invention relates to an apparatus for conveying at least one fluid, comprising at least a first fluidic element (10) and a second fluidic element (30) connected to each other for conveying said fluid, and a base plate (24) to which said first fluidic element (10) and said second fluidic element (30) are mounted. In accordance with the invention said base plate (24) comprises at least a first outlet (46) for feeding a leak test agent to the connection area of said first fluidic element (10) and said second fluidic element (30). The invention further relates to a base plate (24) for mounting at least a first fluidic element (10) and a second fluidic element (30) connectable to each other for conveying a fluid. In accordance with the invention said base plate (24) comprises at least a first outlet (46) for feeding a leak test agent to an connection area of said first fluidic element (10) and said second fluidic element (30).

Abstract: Uniformity of a sputtered conductive barrier layer (50) or seed layer (52) across a semiconductor substrate (18, 42) is improved by incorporating a plurality of electromagnets (26) in or around the sputtering chamber (14) which can be independently powered. In other words, each individual electromagnet can be turned on or off, and/or the amount of power being supplied to each electromagnet (and thus the magnetic field generated by each electromagnet) can be varied independently. Further, the sputtering system (10) includes connection to a computer (30) that is either integral to or connected to a metrology tool (28). The metrology tool measures uniformity of a layer deposited by the sputtering system, analyzes the measurements and feeds back information to the sputtering system as to how to vary the power being supplied to the plurality of electromagnets to improve layer uniformity.

Abstract: A donor substrate (12) which is patterned to include a donor mesa (18) is bonded to a receiving substrate (20). In a one embodiment, a bulk portion of the donor substrate is removed while leaving a transferred layer (26) bonded to the receiving substrate. The transferred layer is a layer of material transferred from the donor mesa. A portion of receiving substrate can be processed to form a recess (27, 28, or 32) to receive the donor mesa. Alternatively, the transferred layer can be formed over a dummy feature (46) formed on the receiving substrate, either with or without the use of mesas on the donor substrate. In a preferred embodiment, the transferred layer is used to form an optical device such as a photodetector in a semiconductor device. With the invention, bonding can be achieve despite having a non-planar surface on the receiving substrate.

Abstract: A resist layer (34) on a semiconductor wafer (20) is patterned by using a scanning exposure system (50) which provides light, containing pattern information which is intended to be transferred to the wafer. The lithographic system is a step and scan system in which a reticle (16) passes between a light source and a lens system(18). The wafer with the resist layer is passed through a focal plane of the patterned light at a tilt angle (&thgr;). The user selects a desirable range for the depth of the resist to be exposed at the focus of the patterned light. The tilt angle is calculated by taking the arc tangent of the desirable range divided by a width of a slit region (52) of the projected light. The depth of focus increases over standard step and scan techniques.

Abstract: A semiconductor device (10) includes a solder bump (40) that is formed using a gold-free under-bump metallurgy (UBM) (21). In a preferred embodiment, UBM (21) includes a diffusion barrier layer (22) of chromium and a metallic layer (24) of copper. The bump layer metallurgy (31) is deposited directly on the metallic layer, without an intervening gold layer. To overcome problems associated with a native oxide layer (26) which forms on the metallic layer, especially on copper, the bump metallurgy includes a seed layer (32) of tin that is deposited prior to a bulk lead layer (34). The bump metallurgy includes a final metallic layer (36) having sufficient tin to make a bump having approximately 97% Pb and 3% tin.

Abstract: A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M are greater than or equal to 2 and the size of the N by M array is selected such that each of the plurality of BGA substrates (12) maintains a planarity variation less than approximately 0.15 mm (approximately 6 mils). The printed wiring board (11) has a thickness (26) sufficient to minimize planarity variation and to allow a manufacturer to use automated assembly equipment without having to use support pallets or trays.