Abstract: Semiconductor devices (140, 410, 610) are tested or burned-in while in a handling or shipping tray (100, 500, 700) using a test contactor (150, 450, 750, 850, 950) which engages either a cell (120, 520, 720) of the tray or the device itself during testing. A tray having a plurality of devices is moved by a handling system in an initial alignment operation where one or more devices is generally aligned beneath the test contactor. Then, the tray or the test contactor is moved in a vertical direction so that engagement features of the test contactor engage either the tray cell or the device to be tested to bring the device into final alignment for testing. Upon final alignment, contacts (152, 452, 752, 852, 952) of the test contactor physically and electrically contact leads (141, 414, 614) and in-tray testing of the devices is performed. In-tray testing reduces manufacturing cycle and minimizes device lead damage by eliminating pick and place handling of the devices at test.

Abstract: Process for maintaining lead positions within a glass layer of a CQFP semiconductor device by using a magnet during high temperature assembly operations. During lead embed, a magnet (46) is magnetically attached to lead frame (44). Upon reflow of a glass layer (48), leads (50) sink into the glass layer to a height controlled by the height (H) of a protrusion (52) of the magnet. A similar magnet (62) can be used to maintain the lead positions during a high temperature operation used to cure a die attach material (60). Yet another magnet (70) can be used to maintain the positions of leads (50) during a lid seal operation. A common magnet design for use in all thermal operations can instead be used. Use of the magnets restrict movement of the leads within the glass layer when the glass is in a softened state.

Abstract: A non-volatile memory having a control gate (14) and a sidewall select gate (28) is illustrated. The sidewall select gate (28) is formed in conjunction with a semiconductor doped oxide (20) to form a non-volatile memory cell (7). The semiconductor element used to dope the oxide layer (20) will generally include silicon or germanium. The non-volatile memory cell (7) is programmed by storing electrons in the doped oxide (20), and is erased using band-to-band tunneling.

Abstract: In on form, a TEOS based spin-on-glass is made having on the order of 10% to 25% by volume of tetraethylorthosilicate, the equivalent of on the order of 0.1% to 3.0% by volume of 70% concentrated nitric acid, on the order of 60% to 90% by volume of alcohol, and the balance water. The spin-on-glass is applied to a semiconductor substrate and heated in order to densify the spin-on-glass.

Abstract: A method of decreasing resistivity in an electrically conductive layer (23) includes providing a substrate (14), using a high density plasma sputtering technique to deposit the electrically conductive layer (23) over the substrate (14), and exposing the electrically conductive layer (23) to an anneal in an ambient comprised of a plasma (21).

Abstract: A mold tool (40) includes a lower platen (10) and an upper platen (18) which have modified surfaces (16) and (20), respectively. The modified surfaces are formed by implanting an implant species (14) at least into areas of the platens which will be in contact with a molding compound resin. By modifying the surface of the molding tool by ion implantation, the need for cleaning the mold tool is reduced due to lower surface friction and wettability of the modified surfaces. These surface characteristics also facilitate easier release of the molded package from the tool. At the same time, wear resistance of the mold tool is improved due to increased surface hardness.

Abstract: A process for probing a semiconductor wafer involves bringing the bond pads (63) of a semiconductor die (114) into contact with probes (122) of a probe card (120) by moving a probe chuck (110) in the Z-direction. Initial contact is made with "zero-overdrive." The probe chuck is then moved in a small amount in the Z-direction to induce a pressure in the probe. Scrubbing of the probes against the pads is then performed by moving the probe chuck in the X and Y directions. During movement in the X and Y directions, the pressured induced in the probe is released, causing the probe to begin to break through an oxide layer (62) of the bond pad. If the oxide layer is not completely broken, the movement of the probe chuck in the Z and then X & Y directions is repeated until electrical contact between the probes and the bond pads is made.

Abstract: Solder bumps are formed on a substrate, such as a semiconductor die (28) or wafer, using a screen printing and reflow operation. Solder paste (18) is screened into openings (14) of a stencil (10). The paste is reflowed within the stencil to produce a solder preform (22). The stencil and solder preforms are then aligned over the substrate to be bumped so that the preform aligns with a metal pad (30) on the substrate. The solder preforms are again reflowed, and the solder within the openings of the stencil is drawn onto the metal pad. To facilitate the transfer of the solder from the stencil to the metal pad, a second stencil (12) can be used to form a protrusion (27) on the solder preform. The protrusion contacts the metal pad during the transfer reflow operation to facilitate removing the solder from the stencil.

Abstract: A method for determining the cleanliness of a surface of a substrate involves using a visual pattern (17, 29). The visual pattern is either provided in the optical portion of a visual system or is formed on the surface of the substrate to be analyzed. A liquid droplet (26, 27) is dispensed onto the substrate surface, and the extent of the spread area of the droplet is compared to the visual pattern. If the area of the droplet is greater than or equal to a tolerance as signified by the pattern markings, then the surface of the substrate is determined to be sufficiently clean. In relying upon a simple visual comparison of the area of the surface covered by the droplet with an empirically determined visual pattern, a method for analyzing surface cleanliness is consistent between operators and surfaces, is easy to set up and operate, and improves manufacturing throughput.

Abstract: A ball grid array semiconductor device (30) includes a plurality of conductive balls (36) and a plurality of conductive castellations (18) around its periphery as redundant electrical connections to a semiconductor die (12). During testing of the device in a test socket (50), the conductive castellations are contacted by test contacts (54). The test contacts do not come in physical contact with the conductive balls. As a result, when testing is performed at elevated temperatures near the melting point of the conductive balls, the conductive balls are not deformed by the test contacts, thereby eliminating cosmetic-defects. Additionally, the absence of physical contact between the conductive balls and the test contacts during testing reduces the likelihood that conductive balls will inadvertently fuse to the test socket or create solder build-up on the test contacts.

Abstract: An apparatus(19) for holding a testing substrate in a wafer prober (16) has a plate (34) hinged to a head stage (18) of the equipment. The plate has two concentric openings to form a ledge (35) for holding the testing substrate (10). Additionally, the ledge has two asymmetrically placed locating pins (38) to allow automatic alignment of the testing substrate which has corresponding alignment holes. A latch (36) locks the plate against the head stage to securely fix the testing substrate in place so that it can make and maintain contact with a pogo pin area (26) on the head stage. The tester also has a wafer support chuck (20) upon which a semiconductor wafer (22) is placed with its active surface up. The head stage of the tester is closed so that the testing substrate contacts the active surface of the semiconductor wafer, and electrical testing may then be performed on the semiconductor wafer.

Abstract: A semiconductor device (30) includes a bumped semiconductor die (32) having a plurality of input/output (I/O) bumps (36) and a plurality of alignment bumps (38). Alignment bumps (38) are formed at the same time as I/O bumps (36) and are used by a vision system to properly align die (32) to a mounting substrate (34) for attachment thereto. Because the alignment bumps are smaller than the I/O bumps, the alignment bumps are not damaged during manufacturing operations such as wafer probe, burn-in, or test, and therefore maintain their original shape. The vision system can thus use the alignment bumps to repeatedly and accurately align the die to the mounting substrate, thereby eliminating misalignment caused by damage to the I/O bumps.

Abstract: A method for forming vias in a semiconductor device improves the resistance and reliability of contacts formed by use of an etch stop layer during the via formation process. An etch stop layer (40), preferably a silicon nitride or aluminum nitride layer, is deposited over conductive interconnect (34). A via (44) is etched in interlayer dielectric (42), stopping on etch stop layer (40). Etch stop layer (40) is then anisotropicly etched to expose the top of conductive interconnect (34), while maintaining a portion of the etch stop layer along a sidewall of the interconnect, and particularly along those sidewall portions which contain aluminum. A conductive plug (54) is then formed in the via, preferably using one or more barrier or glue layers (50). Formation of a tungsten plug using tungsten hexafluoride can then be performed without unwanted reactions between the tungsten source gas and the aluminum interconnect.

Abstract: A method for packaging an integrated circuit begins by providing an organic substrate (310) having at least one device site (312). Within each device site, one or more electronic devices (532) is mounted. Around the device site, slots (316) and corner holes (318) are formed. In one embodiment, a negative feature, such as a notch (326), is formed in the substrate along the inner edge (315) of the slots. After the electronic device is mounted and encapsulated in a plastic package body (320), the device is excised from the substrate by punching corner regions of a final package perimeter (317). The placement of the slots, corner holes, and notches results in a punch periphery that is free from burrs, provides maximum active interconnect area, and minimizes surface and/or edge damage during the punch operation. Instead of forming notches, a positive feature, such as a protrusion (426) can be incorporated into a punching tool segment (428) to provide the same benefits.

Abstract: A TAB semiconductor device (98) is manufactured with a TAB tape (62') which provides an intrinsic standoff for the device. The tape (62') has a carrier film (66'), having at least one cavity, and a plurality of conductors (64) on the top surface of the carrier film. A semiconductor die (42) is substantially centered either inside or below the cavity in the film. The conductors overlie bonding sites (44) on the active surface of the die. Inner-lead-bonds are made between the conductors and the bonding sites, wherein the conductors bend at the edges (65') of the cavity in order to contact the bonding sites, thus concurrently achieving a downset during the action of bonding. An encapsulant (99) provides protection to the die, the inner-lead-bonds, and a portion of the conductors.

Abstract: A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region. (e.g. doped region 52) and the trench isolation region. During formation of opening using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at a corner region (58) of the trench to prevent exposing the junction. By protecting the junction, subsequent formation of a conductive plug (60) will not electrically short circuit the junction, and will keep diode leakage to within acceptable levels.

Abstract: A molding method is used to mold a semiconductor device within a molded carrier ring. A mold tool (30) has an upper platen (32) and a lower platen (34). Each platen has a package cavity (36) and a carrier ring cavity (38). Between the package and ring cavities is a venting hole (60) having a venting pin (63) slidably fit therein. The venting pin includes a flat surface (64) that allows air which is forced from the package cavity during molding to escape through a narrow gap. The gap size is made small enough to prevent the passage of resin to flow through. Thus, the invention permits the mold tool to be compression cleaned and prevents mold tool down-time previously experienced when molding resin gets dogged in traditional venting holes. In another embodiment, the venting pin can be placed within the package cavity and also serve as an ejector pin.

Abstract: A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region (e.g. doped region 52) and the trench isolation region. During formation of opening using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at a corner region (58) of the trench to prevent exposing the junction. By protecting the junction, subsequent formation of a conductive plug (60) will not electrically short circuit the junction, and will keep diode leakage to within acceptable levels.

Abstract: An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.

Abstract: Electronic components are shielded from electromagnetic interference (EMI) by one or more conformal layers filled with selected filler particulars for attenuate specific EMI frequencies or a general range of frequencies. Shielding is accomplished through the use of a single general purpose shielding layer, or through a series of shielding layers for protecting more specific EMI frequencies. In a multilayer embodiment, a semiconductor device (50) is mounted on a printed circuit board substrate (16) as a portion of an electronic component assembly (10). A conformal insulating coating (24) is applied over the device to provide electrical insulation of signal paths (e.g. leads 54 and conductive traces 18) from subsequently deposited conductive shielding layers. One or more shielding layers (60, 62, and 64) are deposited, and are in electrical contact with a ground ring (56).