Abstract: A two step wire bonding process is used to ultrasonically attach a wire (18) to a contact pad (13) on a semiconductor device (10). A first step is used to flatten a rounded tip (19) of the wire (18), and to start the bonding process. This is accomplished by applying a relatively large force to the rounded tip (19), and a relatively low vibrating displacement to the flattened wire tip (19). During a second step the large force is reduced, however; the vibrating displacement is increased. The total time for the two step wire bonding process is slightly less than a prior art one step process.

Abstract: A method of manufacturing a semiconductor component includes depositing a first electrically conductive layer (675) over a substrate (270), forming a patterned plating mask (673) over the first electrically conductive layer, coupling a first plating electrode (250) to the first electrically conductive layer without puncturing the plating mask, and plating a second electrically conductive layer onto portions of the first electrically conductive layer. A plating tool for the manufacturing method includes an inner weir (220) located within an outer weir (210), an elastic member (230) over a rim (211) of the outer weir, a pressure ring (240) located over the rim of the outer weir and the elastic member, and a plurality of cathode contacts (250, 251, 252, 253) located between the pressure ring and the outer weir. The substrate is positioned between the elastic member and the pressure ring.

Abstract: A semiconductor device (40, 50, 70) is electrically connected to a circuit board (30) through use of one or more connectors (10, 20, 90). Connector (10) includes locking pins (14) which fit through alignment holes (34) of the circuit board and which are either mechanically deformed to lock the pins in the holes, or which are received by locking holes (24, 94) of a complementary connector (20, 90). An interposer (60, 80) is used as a compliant member to assure that adequate electrical connection is made between the external terminals (42, 72) of the semiconductor device without damaging the device or the circuit board. Connector (10) includes a cavity (12) which is dimensioned to accommodate the semiconductor device while assuring proper alignment between the locking pins, the external terminals, and the circuit board.

Abstract: Conductive bumps (32) are formed to overlie a semiconductor die (11). The conductive bumps (32) typically have reduced levels of lead, flow at a temperature no greater than 260° C., and have reduced problems associated with alpha particles. In one embodiment, the conductive bump (32) includes a mostly tin (20) with a relatively thin layer of lead (30). The lead (30) and a portion of the tin (20) interact to form a relatively low melting solder close to the eutectic point for lead and tin. Most of the tin (20) remains unreacted and can form a stand off between the semiconductor die (11) and the packaging substrate (42). Other metals and impurities can be used to improve the mechanical or electrical properties of the conductive bumps (32).

Abstract: A dual inlaid copper interconnect structure uses a plasma enhanced nitride (PEN) bottom capping layer and a silicon rich silicon oxynitride intermediate etch stop layer. The interfaces (16a, 16b, 20a, and 20b) between these layers (16 and 20) and their adjacent dielectric layers (18 and 22) are positioned in the stack (13) independent of the desired aspect ratio of trench openings of the copper interconnect in order to improve optical properties of the dielectric stack (13). Etch processing is then used to position the layers (16) and (20) at locations within the inlaid structure depth that result in one or more of reduced DC leakage current, improved optical performance, higher frequency of operation, reduced cross talk, increased flexibility of design, or like improvements.

Abstract: In one embodiment, a conductive interconnect (38) is formed in a semiconductor device by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form an interconnect opening (29). A tantalum nitride barrier layer (30) is then formed within the interconnect opening (29). A catalytic layer (31) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer (30). A layer of electroless copper (32) is then deposited on the catalytic layer (31). A layer of electroplated copper (34) is then formed on the electroless copper layer (32), and the electroless copper layer (32) serves as a seed layer for the electroplated copper layer (34). Portions of the electroplated copper layer (34) are then removed to form a copper interconnect (38) within the interconnect opening (29).

Abstract: An air bag deployment system (20) includes a microcontroller (21), an inflator (23), and an inflator sensor (24). The inflator sensor (24) is adjacent to the inflator (23) and monitors the firing of the inflator (23). The inflator sensor (24) monitors the firing of a squib (36) of the inflator (23). The inflator sensor (24) transmits an inflator firing signal to the microcontroller (21) when the squib (36) of the inflator (23) is activated. In the absence of the inflator firing signal, a backup firing signal is generated by the microcontroller (21) and is transmitted to a backup squib (37).

Abstract: An edge detector (10) detects edges of clock pulses in a digital signal and provides edge detect pulses to a state corrector (20). A state sequencer (15) receives a clock signal and steps through a sequence of states in accordance with the clock signal to generate a recovered clock signal which is substantially synchronized with the clock pulses in the digital signal. The state corrector (20) selectively providing reset states to reset the state sequencer in accordance with various parameters to maintain synchronization between the clock pulses in the digital signal and the recovered clock signal. The state corrector (20) also inhibits resetting the state sequencer (15) when edge detect pulse produced from instability in the edge detector (10) are received.

Abstract: Programmable cells (22, 24, 26, 28) may have discontinuous storage elements (228, 248, 268, 288) as opposed to a continuous floating gate. Each cell further includes first and second current carry electrodes (222, 226, 242, 246, 262, 266, 282, 286) and a control gate electrode (224, 244, 264, 284). In one embodiment, potentials for programming can be selected to program a programmable cell relatively quickly without the need for relatively high potentials. Alternatively, programming can be achieved by flowing current in one direction and then in the opposite direction. In some embodiments, time-variant signals can used during an operation. Embodiments of the present invention can be used with different types of programmable cells including those used in memory arrays and in field programmable gate arrays.

Abstract: Apparatus and a method of cold cross-sectioning soft materials includes providing a chuck attached to a drive motor with a composite plate attached to the chuck and including a heat insulating portion, a heat conducting layer, and a central axially extending duct with a plurality of radially extending conduits in communication therewith, the central axially extending duct is accessible externally for introducing a cooling liquid thereto. A sheet of grinding material is magnetically attached to the composite plate and the drive motor is activated to rotate the composite plate and grinding material. A cooling liquid is introduced into the duct and communicated to the conduits and a lubricant is supplied to the exposed rotating surface of grinding material.

Abstract: An optical semiconductor component includes a semiconductor substrate (120) and a packaging material (140) located over the semiconductor substrate. The packaging material includes an optically transparent cycloaliphatic polymer (142, 242, 400, 600). A method of manufacturing the component includes nixing a monomer (300, 500) of the polymer with a catalyst to form the packaging material, filtering the packaging material, applying the packaging material, and curing the packaging material.

Abstract: A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (20) over a substrate (20). The MOS metallic gate electrode layer (20) is covered with an ARC layer (22). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (22 and 20) are then selectively masked photoresist (24) that is selectively exposed to deep ultraviolet (DUV) radiation (28). The ARC layer (22) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.

Abstract: The present invention provides a means for clearing or wiping the contents of a RAM array without the need for overly large transistors and without experiencing current spikes by using a progressive row-by-row clearing operation. In reference to FIGS. 4 and 5, progressive row clearing is achieved by the addition of a transistor (72) in series with the row RAMWIPE transistor (e.g. transistor 69) in each row. Transistor 72 is gated by a signal PRS (Previous Row Select). PRS for a given row will be asserted or enabled only when the previous row in the array is also selected or enabled. A given row is only selected for clearing in a wipe operation when both a RAMWIPE signal and a PRS (previous row select) signal are asserted. The next row, therefore, is not cleared until the previous row is cleared.

Abstract: A method for writing data to non-volatile memory (50) involves alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). After writing, a verify erase (VE) operation and a verify program (VP) operation are performed to determine if multiple cycles are necessary. The method also permits refreshing data in the array without transferring the data onto a data bus for improved security. In one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete. The memory cell structure allows isolation of each bit in the array to avoid adverse effects on neighbor bits.

Abstract: A process for fabrication of a multilevel interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to fill the via opening (14) at the bottom of an interconnect channel (24). Selective deposition is enhanced by the use of a nucleation layer (20) which is formed on the bottom of the via opening, without being formed on the sidewalls, by use of directional deposition technique such as inductively coupled plasma (ICP) deposition. Nucleation layer (20) eases requirements of a cleaning operation prior to selective deposition and provides a surface from which void-free selective growth can occur.

Abstract: Conductive plugs (28) are formed in a semiconductor device (10) using a chemical mechanical polishing (CMP) process. A blanket conductive layer (26), for example of tungsten, is deposited in a plug opening (24). The conductive layer is polished back by CMP using a slurry comprised of either copper sulfate (CuSO.sub.4) or copper perchlorate [Cu(ClO.sub.4).sub.2 ] and an abrasive, such as alumina or silica, and water. In another embodiment, a CMP process using such slurries may be used to form conductive interconnects (50) in a semiconductor device (40).

Abstract: A method for testing a bumped semiconductor die (14) is accomplished without excessively deforming the conductive bumps (200). In one form, testing is accomplished using a test contactor (12) which includes a deformable layer (204), such as an elastomer, which is patterned to include a plurality of openings (202) corresponding in pattern to the conductive bumps (200). The die is positioned next to the test contactor and the two are compressed together. The walls of the openings in the elastomeric material constrain the deformation of the conductive bumps in the X-Y plane due to the lateral pressure exerted on the sides of the conductive bumps. In a second form, a mechanical standoff (216) limits the extent to which the die and the test contactor can approach, thereby limiting the deformation in the Z-axis. In a third form, both elastomeric material and mechanical standoff act to constrain the deformation in the X-, Y-, and Z- axes.

Abstract: Particles counts and concentrations are reduced from the backside of a substrate, such as a semiconductor wafer or flat panel display with the invention, to improve precision and uniformity in subsequent operations, including lithography operations. A semiconductor substrate is placed on a chuck (10) in a track system (30), such as a resist coater, a developer, or other form of spin coater. The substrate is processed accordingly to conventional practice and the substrate is removed. The chuck is then cleaned by dispensing a solvent, for example using EGMEA or PGMEA, through a dispense nozzle (38) of the system. Alternatively, or additionally, a brush (36) or sponge which is at least partially saturated with a solvent (39) is moved across the chuck to remove particles. The chuck cleaning can occur between every wafer, every wafer lot, or less periodically, such as between shifts, as the chuck particle accumulation dictates.

Abstract: A loop cache (26) is used in a data processing system for supplying instructions to a CPU to avoid accessing a main memory. Whether instructions stored in the loop cache can be supplied to the CPU is determined by a distributed TAG associated with the instruction address computed by the CPU. The instruction address includes an LCACHE index portion (42), an ITAG portion (44), and a GTAG (46). LCACHE index (42) selects corresponding locations in each of an ITAG array (50), an instruction array (52), and a valid bit array (54). A stored GTAG value (48) is chosen irrespective of where LCACHE index (42) is pointing. The GTAG portion of the instruction address (40) is compared to the stored GTAG value (48). The ITAG portion (44) of instruction address (40) is compared with the indexed ITAG of the ITAG array (50). If both the GTAG and ITAG compare favorably, the instruction is supplied from the loop cache to the CPU, rather than from main memory.

Abstract: A polishing system (10) is used to polish a semiconductor wafer (16) in accordance with the present invention. Polishing system (10) includes a wafer carrier (14) which includes a modulation unit (20). Modulation unit (20) includes a plurality of capacitors made up of a flexible lower plate (22) and a plurality of smaller upper plate segments (24). A controller (40) monitors the capacitance between each smaller upper plate segment (24) and lower plate (22), and compares the measured capacitance against a predefined set capacitance. To the extent the measured capacitance and predefined capacitance are different, controller (40) adjusts the voltage being applied to the respective upper plate segment (24) so that the measured capacitance and predefined capacitance are aligned. Thus, the present invention is able to achieve dynamic and localized control of the shape of the wafer as it is being polished.