Abstract: Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

Abstract: Nitrogen is piled-up at a top interface of a gate dielectric layer by a process of the present invention. A gate dielectric layer (14) is formed on a substrate (12). A buffer layer (16), such as polysilicon, is formed on the dielectric layer. A nitrogen source layer (18), such as oxynitride, is formed on the buffer layer. The device is annealed to drive nitrogen from the source layer through the buffer layer and to an interface (15) between the polysilicon and the dielectric, resulting in a high nitrogen concentration at this interface. A nitrogen concentration may also be achieved at an interface (13) between the dielectric layer and the substrate.

Abstract: A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.

Abstract: A silicon nitride layer (34) has improved adhesion to underlying copper interconnect members (30) through the incorporation of an intervening copper silicide layer (32). Layer (32) is formed in-situ with a plasma enhanced chemical vapor deposition (PECVD) process for depositing silicon nitride layer (34). To form layer (32), a semiconductor substrate (12) is provided having a desired copper pattern formed thereon. The copper pattern may include copper interconnects, copper plugs, or other copper members. The substrate is placed into a PECVD reaction chamber. Silane is introduced into the reaction chamber in the absence of a plasma to form a copper silicide layer on any exposed copper surfaces. After a silicide layer of a sufficient thickness (for example, 10 to 100 angstroms) is formed, PECVD silicon nitride is deposited. The copper silicide layer improves adhesion, such that silicon nitride layer is less prone to peeling away from underlying copper members.

Abstract: A semiconductor (30) is shielded from electromagnetic interference by a combination of a reference plane (22) of a circuitized substrate (12) and two different encapsulants. The first encapsulant (38) is an electrically insulative encapsulant which mechanically protects a semiconductor die (32). The first encapsulant is constrained by a dam structure (40) so as not to encapsulate conductive reference pads (18) which are electrically connected to the reference plane by conductive vias (20). A second encapsulant (42) is dispensed over the first encapsulant and is in contact with the reference pads. The second encapsulant is an electrically conductive encapsulant, and is preferably made of a precursor material having the same or similar properties as that of the first encapsulant, but is filled with conductive filler particles to establish electrical conductivity of the encapsulant.

Abstract: A layer of material (14) comprising silicon, such as an SiO.sub.2 layer, overlying a silicon substrate (12) of a semiconductor device (10), is dry etched without the need for traditional halocarbon gases (such as CHF.sub.3, CF.sub.4, and C.sub.2 F.sub.6) which are known green-house gases. A fluorine source, for producing the active fluorine radicals needed to etch silicon, is selected from either HF or F.sub.2 gases. A carbon-oxygen source, for providing and stabilizing polymer build-up in the reactor, is selected from either CO or CO.sub.2. An additional hydrogen source may be added as needed.

Abstract: A semiconductor device (10) includes a lead frame (12) having tie bars (16). In one form of the invention, the tie bars are used to support a semiconductor die (20) to alleviate package cracking problems caused by stress and to provide a universal lead frame which is suitable for use with many different die sizes. In another embodiment, a semiconductor device (45) includes a lead frame (40) having a mini-flag (42) to accomplish these same objectives.

Abstract: A semiconductor device (10) has a thin-film transistor (TFT) formed in and around an opening (24) in a dielectric layer (22). A conductive layer (26) lines the opening sidewalls and serves as a gate electrode of the transistor. A conductive layer (30) is deposited over the gate electrode to form a source region (32), a channel region (36), and a drain region (34). The two conductive layers are separated by a gate dielectric (28). Because both the gate electrode and the channel region conform to the opening sidewalls and bottom, the entire channel region is under direct gate control. Device (10) may also include a conductive region, such as a gate electrode (15) of a bulk transistor, at the bottom of opening (24) and in electrical contact with the TFT gate electrode.

Abstract: Accuracy and repeatability of atomic force microscopy (AFM) are improved by coating a single crystal silicon probe tip with a layer of carbon. The carbon-coated probe tip is brought into contact with a specimen surface, and is scanned across the area of interest. The carbon coating improves the interaction between the probe tip and specimen surface, particularly insulating surfaces, by reducing probe tip damage and minimizing charge build-up.

Abstract: A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.

Abstract: Deformation of TAB tapes due to temperature changes is prevented by thermo-mechanical leads. In one embodiment of the invention, a semiconductor device (30) includes an electronic component (31) and a TAB tape. The tape includes a carrier film (12) and electrical leads (20) formed on the carrier film. The electrical leads are electrically coupled to the electronic component. Also included on the carrier film are thermo-mechanical leads (32) which are formed in opposing regions of the carrier film, regions which are typically void of leads. The thermo-mechanical leads have approximately the same lead pitch as the electrical leads in order to provide a uniform distribution of stresses across the TAB tape upon exposure to varying temperatures.

Abstract: A method of encapsulating a semiconductor device permits use of the same mold for various package types. In one form, a mold (34 and 36) has a first cavity (50) in which a first insert (52 and 53) is positioned, the first insert defining a length and a width of a package body which is to be formed in the mold. The first insert in the first cavity also defines a second cavity (54) in which a second insert (56 and 57) is positioned, the second insert defining a thickness of the package body. Plastic is inserted into the mold to form the package body. To form other package types, one or more inserts are replaced instead of using a different mold. In another embodiment, the inserts are adjustable. For example, rather than having to change inserts to form a package with a different thickness, the inserts are adjusted by, for instance, a screw mechanism (66) within the mold or by the addition or removal of shims (60).

Abstract: A semiconductor device (10) includes a voltage distribution ring (20) attached to a plurality of leads (16). The ring is made up of an insulating layer (24), preferably polyimide, and a metal layer (22), preferably gold-plated copper foil. The ring may also include intervening adhesive layers (not illustrated). The ring surrounds a semiconductor die (12) and is electrically coupled to bond pads (14) of the die by wire bond (18). In various embodiment of the invention, the ring may be segmented to distribute two different voltages, such as power and ground; the ring may include slots to expose underlying portions of the leads; and the ring may be attached to either the top surface or bottom surface of the leads.

Abstract: A semiconductor device has test-only contacts to reduce the size of the device and eliminate unnecessary external contacts. In one form of the invention, a semiconductor device (30) is provided with solder balls (26) which are electrically coupled to those portions of a semiconductor die (20) that are necessary for device operation. The device also includes test pads (32) formed on a package substrate (12) which are electrically coupled to those portions of the die which are necessary only for a manufacturer's testing purposes. In another form, a semiconductor device (10) includes external test-only solder balls along the periphery of the package substrate, for example solder balls between boundaries A and B. After testing is complete, the package substrate is excised along boundary A, thereby eliminating solder balls which are not needed by the device user. A combination of the two techniques may also be used.

Abstract: A semiconductor device has structures to reduced stress notching effects in conductive lines. In one form, the semiconductor device includes a semiconductor die which has a plurality of active conductive lines thereon. The plurality of conductive lines collectively has a first and a second outside edge. In close proximity to each of the first and the second outside edges is a stress reducing line. Each of the stress reducing lines is a non-active structure (in other words does not transmit signals) and functions to reduce stress concentrations on the plurality of active conductive lines which are imposed by overlying insulating and passivation layers. As a result of weakened stress concentrations, the amount of stress notching in the active conductive lines is reduced.

Abstract: A lead-on-chip (LOC) semiconductor device (10) has an integral decoupling capacitor in the form of a capacitor tape (20) attached to an active surface (14) of a semiconductor die (12). The capacitor tape includes two adhesive layers (22 and 24) to bond the die to the capacitor tape and to a plurality of leads (18). The tape also includes two conductive layers (26 and 28), made for instance of copper foil, which serve as the two electrodes of the capacitor. The electrodes are separated by a dielectric layer (30) which in one embodiment comprises barium-titanate (BaTiO.sub.3). The electrodes of the capacitor are electrically coupled to appropriate power and ground leads of the device by bonding wires (36 and 40) and to appropriate bonding pads (16) also by bonding wires (38 and 42). The bonding wires can be configured using any of three available wiring options. The present invention can also be implemented in a chip-on-lead (COL) device.

Abstract: Deformation of TAB tapes due to temperature changes is prevented by thermo-mechanical leads. In one embodiment of the invention, a semiconductor device (30) includes an electronic component (31) and a TAB tape. The tape includes a carrier film (12) and electrical leads (20) formed on the carrier film. The electrical leads are electrically coupled to the electronic component. Also included on the carrier film are thermo-mechanical leads (32) which are formed in opposing regions of the carrier film, regions which are typically void of leads. The thermo-mechanical leads have approximately the same lead pitch as the electrical leads in order to provide a uniform distribution of stresses across the TAB tape upon exposure to varying temperatures.

Abstract: A semiconductor device (20) makes contact between a first metal line (22) and an overlying second metal line (24) without the need for a conductive landing pad. Sidewall spacers (30) are formed adjacent sides of metal lines (22) such that during formation of a via (34) in an overlying dielectric layer (32), the sidewall spacer prevent trenching of underlying dielectric layer (28) if the via is misaligned. The sidewall spacers are formed of a dielectric material which has an etch rate which is significantly slower than the etch rate of dielectric layer (32). In another embodiment, portions of the sidewall spacers are selectively removed prior to depositing a second metal layer (42). Upon depositing the second metal layer, the side of metal line (22) is locally clad with the second metal to increase contact area and lowering contact resistance.

Abstract: Conductive balls (44), preferably solder balls, are attached to pads (32) on a substrate (30) using a vacuum pick-up tool (34). The pick-up tool lowers the conductive balls into a bath of flux (48) without allowing the balls to touch the bottom of a recess (47) in a flux plate (46), thereby reducing the likelihood of dislodging the solder balls from the pick-up tool. The pick-up tool withdraws the balls from the flux, and aligns the balls with the respective pads on the substrate. Once positioned, the balls are released from the pick-up tool. A reflow operation metallurgically bonds the balls to the pads.

Abstract: A pad array semiconductor device (35) includes a thermal conductor (28) integrated into a circuitized substrate (14). A semiconductor die (12) is mounted on the substrate overlying the thermal conductor to establish a thermal path away from the die. The thermal conductor may also be covered or surrounded by a metallized area (37, 39), which together may serve as a ground plane in the device. Preferably one or more terminals (26) are attached to the thermal conductor for improved thermal and electrical performance. One method of integrating the thermal conductor in the substrate is to position a metal plug into an opening 30 of the substrate. The plug is then compressed or otherwise plastically deformed to fill the opening and create a substantially planar substrate surface.