Abstract: A clock deskew circuit comprises a variable delay module and a control module. Included in the variable delay module are an input terminal for receiving a digital input clock signal, a control terminal for receiving an analog control signal, and a delay circuit which propagates the input clock signal from the input terminal to a buffer such that certain type signal edges (i.e., rising edges or falling edges) are delayed for a time interval which is varied in a continuous fashion by the magnitude of the control signal. Included in the control module is a feedback lead which receives the delayed clock signal from the buffer of the delay module, another lead which carries the input clock signal, and a control signal generating circuit.

Abstract: A method of tracking incomplete writes in a disk array includes the steps of sequentially receiving a plurality of write commands which identify respective blocks in the array that are to be written; generating a list of expanded write areas for only those write commands which are received most recently, where each expanded write area encompasses the blocks that are to be written plus additional blocks which are likely to be written by subsequent write commands; modifying the list, each time a write command is subsequently received which writes a particular block that is not in any expanded write area in the list, by replacing one expanded write area with a new expanded write area that encompasses the particular block; and storing a replica of the list on a magnetic media each time the modifying step occurs.

Abstract: A computer network serviced by a maintenance subsystem holds a control processing module (CPM) holding a Data Path Array as interface to a main memory module and I/O Module. A maintenance controller in the CPM has a preloaded Flash Memory unit holding all the necessary operating addresses and data which can be rapidly transferred via a special wide parallel high speed data bus to a data path array unit for subsequent conveyance to a channel microcode block in a main memory module. The operating data include channel microcode data necessary for the I/O Module to communicate with different types of peripheral devices.

Abstract: A method of transferring funds electronically, is performed by a group of N computers X(1) thru X(N) which are intercoupled to each other, and to another computer Y, by a communication channel. Each computer of the group includes multiple customer accounts, and the computer Y includes a net account for each computer of the group. To initiate the transfer of funds between two customer accounts, a customer sends an input request to one of computers X(i) of the group; and this input request specifies that funds F(z) be transferred in a particular direction between a customer account A(r) in computer X(i) and a customer account A(s) in another computer X(j) of the group. For each input request that is received by computer X(i), a respective sequence of electronic control messages is sent on the communication channel among the computers X(i), X(j) and Y.

Abstract: A method is provided in a server for storing and retrieving files of various formats in an object database coupled to a network including a multiplicity of clients also coupled to the network. The server includes a storage device for storing objects of the database. The method begins by determining the type and content of files received by the server from the clients coupled. Each file received by the server is transformed into an object. The transformed objects are stored in a hierarchy in accordance with the type and content thereof. The retrieving part of the process includes transmitting a "get" request to the server; searching a Virtual File class for an object whose name matches the file name; and examining corresponding properties of the matching object for compatibility with the first parameter. If compatible, a next parameter is examined for corresponding properties for compatibility.

Abstract: A central processing module (CPM) uses a data path array interface connecting dual system busses to a main memory module and I/O module. A maintenance controller in the CPM manages a programmable array logic unit controller to read out microcode words in the main memory module to verify their accuracy by comparison with an original data base of microcode words in a flash memory which was earlier pre-loaded from a maintenance subsystem. A high speed auxiliary data bus controlled by the programmable array logic controller, provides a high speed transfer channel for moving the main memory words to the maintenance controller which can then institute a verification procedure for each memory word.

Abstract: A content server using an object database supports a network of multiple User clients. The database is loaded with virtual objects which constitute source documents in the form of a multiplicity of resource objects, which may be file-oriented objects or message-oriented objects, which enable the format of any source document to be converted to another format compatible for transport via an appropriate protocol to a requesting client User. The resource objects include a multiplicity of converter objects which are defined and placed in the database to provide format transformation from the format of the original source document content into the format required by a calling requester. The object database will be searched to find the proper converter object to transform the contents of the source document into the required format for the calling requester's facilities or for transmittal to a digital appliance in a protocol appropriate to the receiving requester or digital appliance.

Abstract: A method in a repository coupled to a computer system that generates OLE automation and Interface Definition Language ("IDL") interfaces from metadata (i.e., information about data). Visual Basic programming language is used to develop a tool that generates the automation binding from the metadata in the repository. The method extends C++ programming language binding across networks, independent of the Object Request Broker (ORB) being used. A schema is provided that maps the types and features of a repository to OLE automation and member functions for Windows. The method also integrates the Application Programming Interface (API) of a repository with Windows scripting programming languages through Object Linking and Embedding (OLE).

Abstract: A computer architecture where a processor with store-through cache is linked with a cache control module, a bus interface to dual system busses, a system spy module monitoring the dual system busses for new data overwrites and an invalidation queue for holding cache addresses to be invalidated while the entire network is controlled by a programmable state machine system for enabling cache access and cache invalidation operations.

Abstract: A temperature control system comprises: an electric heater that has a first face which contacts an electronic device, and a second face which is opposite the first face; a heat sink, coupled to the second face of the heater, which absorbs heat from the electronic device through the heater's second face; respective temperature sensors coupled to the heater and the heat sink; and an estimator circuit, coupled to the temperature sensors. The estimator circuit estimates the temperature of the electronic device as a function of the sensed heater and heat sink temperatures, and that enables the device temperature to be regulated even through the device does not have a temperature sensor. By electrically controlling just the heater power, heat flow to/from the electronic device is quickly adjusted; and that in turn quickly regulates the device temperature.

Abstract: Solder balls are placed onto multiple I/O pads of an integrated circuit package by the steps of a) providing a template with a channel which has multiple openings on a surface of the template that match the pattern of the I/O pads; b) pouring a plurality of the solder balls onto the surface of the template; c) vibrating the template and thereby seating a respective solder ball in each of the template openings; d) turning the template over, after the vibrating step and while a vacuum is applied to the channel, to remove excess solder balls from the template; and e) removing the vacuum from the channel when the solder balls on the turned over template are aligned to the I/O pads of the integrated circuit package. Due to the vibrating step, the solder balls settle in the template openings in a position where vacuum leaks past the solder balls become minimized; and that stops the solder balls from dropping out of the template openings when the template is turned over.

Abstract: A hardware message transfer control unit designated as the Auxiliary Message Arbitrator Unit (AMA) manages message transfers and transfer protocols in a network of sending and receiving digital hardware modules. Flexibility of network expansion to include software emulated digital modules to the hardware modules is provided in RAM circuitry at the message transfer control unit.

Abstract: A multi-set cache structure, providing a first-level cache and second level cache to a processor, stores data words where each word holds two bytes and two status bits. Each cache set includes a Tag RAM for holding the address data words and a Parity RAM holding a parity bit for each byte and a parity bit for the two status bits. A programmable array logic control unit has a predictive generator logic unit to generate the proper "status parity bit" for each set of status bits (V,R) without need for waiting to calculate the status parity bit from the existing values of the two status bits.

Abstract: A computer network having a Control Processing Module (CPM) maintained by an external Maintenance Subsystem where the CPM has JTAG compatible digital units, but where the Cache Module is not JTAG compatible. Specialized transceivers having Boundary Scan Registers are activated to enable loading of address words in a Tag RAM while concomitantly placing correct initial parity data in a Parity RAM without need to continue communication with the external Maintenance Subsystem. The Boundary Scan Registers in said transceivers are set up to perform as up-counters to sequence through all address locations in the Tag RAM while a Control PAL calculates and places the associated parity values in each corresponding address location in the Parity RAM.

Abstract: A temperature control system comprises: an electric heater that has a first face which makes contact with an electronic device, and a second face which is opposite the first face; a heat sink, coupled to the second face of the heater, which absorbs heat from the electronic device through the heater's second face; and a temperature sensor, coupled to the electronic device which senses the device temperature T.sub.d. A control circuit is coupled to the device temperature sensor and to the heater; and it decreases the power to the heater when the sensed temperature of the electronic device is above the set point, and vice-versa. When the heater temperature T.sub.h is less than T.sub.d, then heat flows from the electronic device through the heater to the heat sink; and the rate of heat flow increases as T.sub.d -T.sub.h increases. When T.sub.h is more than T.sub.d, then heat flows to the electronic device from the heater; and the rate of heat flow increases as T.sub.h -T.sub.d increases.

Abstract: Multiple I/O pads are arranged in a pattern on a surface of an integrated circuit package, and an obstruction in the package prevents a planer solder flux mask from lying flat on the surface around the I/O pads. Such an obstruction can, for example, be a lid in the package which projects above the I/O pads, or it can be an encapsulant which covers a chip in the package and projects above the I/O pads. Despite the presence of the obstruction, solder flux is dispensed on the I/O pads of the integrated circuit package by the steps of --a) providing a pin block that has a base from which multiple pins project, and the ends of the pins match the pattern of the I/O pads; b) coating the ends of the pins with a solder flux; and, c) transferring a portion of the solder flux from the ends of the pins to the I/O pads by temporarily touching the coated ends of the pins against the I/O pads.

Abstract: A pulse synchronizing module includes: a) a pair of input leads which respectively receive a clock signal and digital input pulses that are asynchronous to the clock signal; b) a first counter circuit which is triggered by rising edge transitions in the input pulses, and a second counter circuit which is triggered by falling edge transitions in the input pulses; c) first and second registers which, in synchronization with the clock signal, sample respective counts in the first and second counter circuits; and d) an output circuit, coupled to the first and second registers. This output circuit generates, the rising edge of an output pulse, in synchronization with the clock signal, when the count sample in the first register differs from the number of rising edges which the output circuit previously generated; and it generates the falling edge of the output pulse, in synchronization with the clock signal, when the count sample in the second register differs from the number of falling edges previously generated.

Abstract: The disclosed invention is a method for generating code in a maintainable form and in performing needed maintenance for the same. This method is useful in a computing system having at least one server and a multiplicity of clients coupled thereto by means of a network. The server includes a CPU executing legacy programs and at least one storage device for storing forms of the legacy program. The generated code implements the host forms while allowing for additional logic to be added. The method of this invention operates in at least one of the clients for generating code for modifying existing event routines for controls on the forms. Moreover, the code generated by the method of this invention is separated from additional logic added by a programmer, and this programmer-added logic is retained even as the generated code is revised.

Abstract: A multi-level distributed data processing system includes: 1) a system bus having a main memory coupled thereto; 2) multiple high level cache memories, each of which has a first port coupled to the system bus and a second port coupled to a respective processor bus; and, 3) each processor bus is coupled to multiple digital computers through respective low level cache memories. Further, each low level cache memory stores data words with respective tag bits which identify each data word as being shared, modified or invalid but never exclusive; and, each high level cache memory stores data words with respective tag bits which identify each data word as being shared, modified, invalid, or exclusive.

Abstract: A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through cache memory which includes interface modules including a spy unit for maintaining cache coherency and arbiter modules so that any particular module is not starved out. A maintenance processor organizes the network as a joined system where both the store-through and non-store through processor units can utilize either one of the dual system busses or a split system where one bus is dedicated to the store-through processor units and one bus is dedicated to the non-store through processor units.