Abstract: The present invention is an apparatus for adapting transmissions between an industry standard data bus of a host computer having a host memory and a fiber channel coupled between said host computer and a peripheral storage subsystem having at least one disk drive, which apparatus comprises an interface logic coupled between the industry standard bus and a local bus of the apparatus; a buffer memory coupled to the local bus; a multiplexor/control device coupled to the local bus and being disposed for transmitting therethrough address and data; a fiber channel controller disposed for formatting header and data structures that meet fiber channel protocol, which controller is coupled to the multiplexor/control; a gigabit link module disposed for converting the header and data structures from a parallel format to a serial format and being coupled between the fiber channel controller and the fiber channel; a microprocessor disposed for providing service requests from the host to read and write data from the host me

Abstract: An electronic data transmission system has a low peak-to-average power ratio by including a transmitter circuit which receives an input signal and in response generates a distorted output signal. This distorted output signal is generated by amplifying the input signal with one particular gain when the input signal is at a maximum magnitude which gives the distorted output signal a corresponding maximum magnitude, and by amplifying the input signal with a larger gain when the input signal is in a predetermined range below the maximum magnitude. The distorted output signal travels over a communication channel to a receiver circuit, which regenerates the input signal by amplifying the distorted output signal with a gain that is the inverse of the gain by which the distorted signal is generated.

Abstract: A performance regulator program monitors and controls in real time, the performance level which an application program achieves when it is executed on a digital computer. With this performance regulator program, any external units which are coupled to the computer are prevented from being overloaded by excessive performance in the application program. Also with this performance regulator program, several models of the application program can be easily generated such that each model achieves a different performance level.

Abstract: In accordance with the disclosed invention there is provided a method in a system server for storing and retrieving messages of various formats in an object database coupled to a network including a multiplicity of clients also coupled to the network. The server includes a CPU and at least one storage device coupled thereto for storing objects of the database. The method includes steps for driving a database that solves the problem of transforming incoming messages into objects for storage in the database and organizing the transformed messages into a hierarchy of objects in accordance with the purpose and destination of such incoming messages for storage in the database.

Abstract: A system and method for setting the sequence of processor operations in real time depending on the nature of Write commands and Send Message Commands in waiting queues which are ordinarily sequenced with Read OPs according to the sequential order that the commands are received. The system will give bus access to Read commands ahead of the Write commands and other commands in the waiting queues as long as data coherency will not be affected. Thus, the sequence of bus access can be modified to a different sequence giving priority-of-access to Read commands.

Abstract: A network in which an incoming word of 4 bytes and 4 parity bits is split into an address pointer and Tag address data into a Tag RAM storing two bytes which do not align with the incoming bytes and which leave a 2-bit (x,y,) crossed field. A programmable array logic Control PAL places correct parity values into a Parity RAM for the 2 stored bytes and later recreates the original word of 4 bytes and parity bits by using a flip-bit value (SPX) which simplifies the regeneration of correct parity values.

Abstract: The disclosed invention is a computer-implemented method for registering triggers for processing at the end of each transaction occurring in a database. This method positions a class where a given object exists; and for each trigger in the class, a determination is made if the trigger is in a trigger list of an object link. If it is not, a determination is made if a given object is in an object link of a transaction. If it is not, then the given object is inserted into the object link of the transaction; and then the trigger is inserted in a list of the object link. These steps are repeated until all triggers in the class have been processed. A determination is next made if there is a superclass of the class. If yes, then a superclass, is positioned and the steps are repeated for each trigger in the superclass (i.e., polymorphic trigger). Finally, if no superclass of the class exist, then the method is exited.

Abstract: The method of the present invention is useful in a computer system having a user interface, a CPU, a memory, at least one disk drive and an object database stored in one or more disk drives. The method is used to derive an object database independent standard API from the description of the object in the object database. The method of the present invention, which is executable by the computer system, comprises the following steps: for each database type, TYPE, declared in the database, executing the following steps: opening a file on said at least one disk drive and storing therein the results of the following steps; declaring a surrogate class sTYPE; for each property, PROP, of TYPE, declaring accessors and mutators; declaring construct and destruct member functions; for each operation, OP, of TYPE, declaring member functions; and, declaring special functions.

Abstract: A two domain network linking a first and second data processing system enables efficient data transfers between modules in the first system and modules in the second system through linkage by bus exchange modules having message queues and snoop-write address queues in each domain. Each system also allocates bus access using a selectively adjusting bus access priority arbitration logic unit. The Snoop-Write address queues in each bus exchange module can temporarily hold a sequence of Write OP addresses snooped from one domain for invalidation in another domain without requiring the bus exchange module to dominate its access priority over other requesting modules.

Abstract: The method of the present invention defines a method in a computer system having a user interface, a memory, a repository and a database, and a repository program operating in the computer system for generically manipulating properties of objects stored in the repository. The program executes a method comprising the steps of determining if the current value of the property is known, and if not; determining if the current value of the property is needed, and if so; calling getProperty to retrieve the current value of the property; determining if the value of the property is to be changed, and if so; calling setProperty to alter the value of the property.

Abstract: A system and method for enhancing the rapidity of invalidation cycles in a processor having store-through cache holding 4-word data packets whereby an invalidation queue holds addresses of data to be invalidated in cache and the addresses are supplied by a system bus spy module which monitors the addresses of new data words selected for a write operation.

Abstract: A network comprising a central processing module and maintenance subsystem which provides a system for rapid loading of instruction words in a microcode RAM whereby microcode instruction words from the maintenance subsystem are preliminarily loaded into a flash memory in the central processing module. A maintenance controller transfers the microcode instruction words from the flash memory over a transfer bus to a data path array which connects to a processor-instruction memory bus for enabling microcode addresses and data words to be rapidly transferred into a microcode RAM instruction memory. A programmable controller activated by the maintenance controller in the central processing module then regulates the transfer of data to the microcode RAM by providing incrementation of the addresses of the instruction words on an automatic basis and thus relieving the processor of this function.

Abstract: A cache memory includes: a plurality of tag memory blocks, each of which stores multiple compare addresses; a first bus which sends a low order address to all of the tag memory blocks; a respective output from each tag memory block on which a compare address is read in response to the low order address; a second bus which carries a high order address; and, a comparator circuit which generates a miss signal when the compare address on the output from every tag memory block miscompares with the high order address. Each tag memory block further stores respective control bits with each compare address; and each tag memory block responds to the low order address by reading the compare address and the respective control bits, in parallel, on its respective output.

Abstract: A precision delay circuit in an integrated circuit chip includes a transistor switching circuit in combination with a control circuit and a compensation circuit. The transistor switching circuit receives an input signal; and in response, the transistors switch on and off at an unpredictable speed to generate an output signal with a delay that has a large tolerance. The control circuit estimates the unpredictable speed at which the transistors switch and it generates control signals that identify the estimated speed. The compensation circuit includes a plurality of compensation components for the transistor switching circuit. This compensation circuit receives the control signals from the control circuit; and in response, it selectively couples the compensation components to the transistor switching circuit such that the combination of the transistors and the selectively coupled components generates the output signal with a precise delay that has an insignificant tolerance.

Abstract: An optimization system for the cache-fill operation in a multi-set cache memory operates to select that cache-set which indicates it has invalid data therein and/or also indicates that an associated upper level cache has correspondingly invalid data. When no data invalidity is indicated, then a random counter is used to arbitrarily select an address for one set of the multiple-set cache units for the data-fill operation.

Abstract: The present invention operates in a file server having a peripheral storage subsystem coupled thereto by means of a fibre channel. The file server includes an apparatus disposed between the file server and the storage subsystem for adapting fibre channel transmissions to and from an industry standard data bus of the file server. The apparatus includes a microprocessor executing a method comprising the following steps. Sensing if an interrupt has occurred by the file server, and if so, determining the condition of the interrupt by the file server and handling it. If an interrupt has not occurred, testing an interface between the fibre channel and the apparatus to assure connectivity of the fibre channel. Next, sense for an action to be taken in response to the interrupt, and if so attempt to take appropriate action.

Abstract: A pressure-mountable, electro-mechanical assembly includes a housing which holds an integrated circuit chip in an open cavity; and, the housing has conductors that connect the chip to a pattern of metal pads on an exterior surface of the housing. A lid lies on the exterior surface of the housing, covers the cavity, and has terminal holes that match and expose the pattern of metal pads. Respective conductive springs are held in the terminal holes, contact the metal pads, and project from the lid. This lid operates as both a protective cover for the chip and a carrier for the springs.

Abstract: The method of the present invention is a repository program operating in a computer system for invoking operations on objects stored in the repository. The method assigns a first set of unique numbers for each type in a model library and a second set of unique numbers for each operation in each type. The first and second set of unique numbers are stored in metadata of the repository. Router and helper functions are generated for translating a generic call to an actual C++ procedure at run time using one of the first and one of the second unique numbers, and compiling and linking the router and helper functions in a library of the model. If the operation is invokable, the first and second unique numbers are retrieved from metadata. They are then used with the generated router and helper functions in the library model for invoking the actual C++ procedure.

Abstract: An initiator-sending module requests bus access on a retry-basis after a "bus-error" or "receiver-not ready" situation. The bus request retry is provided with an adjustable wait delay period tailored to the specific system and provides a programmable random wait delay which also includes a minimum time delay period programmed for that specific system network.

Abstract: A computer network is connected via dual system busses to multiple digital modules such as a Central Processing Module with a Central Processor and also to a main memory module, plus an I/O module in addition to other possible modules, such as other Central Processing Modules. The Central Processor has a cache memory which is accessed on the basis of adjustable priorities, the most normal situation being that the Central Processor has first priority to cache access. However, under certain other conditions, the priority of access to cache is adjusted to give priority to an invalidation queue when it is almost full of invalidation addresses to be processed on invalidation cycles to the cache memory. Another priority is given to the invalidation queue after a Read-Lock operator is initiated by the processor. The resulting adjustable priorities work to optimize the integrity and speed of throughput of the system.