Abstract: A method is disclosed that enables changing of print commands for traditional line printers to character highlighting capabilities offered by modern non-impact type printers. The disclosed method provides a technique to look ahead in a stream of data to be printed and determining if a modification of the print is to occur. If so, a table of attributes is provided for indexing to the changed character for transmission to the printer.

Abstract: A multi-set cache module is initiated by a maintenance subsystem to function with all sets on-line or only some sets on-line. A parity error sensing switch flip-flop unit will selectively disable only those sets which indicate parity error problems except when multiple simultaneous "hit" signals occur, in which case, the switch unit disables all of the cache sets.

Abstract: Apparatus and method are provided for preventing access to a memory location while that memory location is being modified, updated, etc. When a peripheral device wishes to accomplish such a change at a memory location, it provides the changed data and its intended memory address to an input/output unit. The input/output unit includes a plurality of separately controlled multiplexers, the number of multiplexers being preferably selected to correspond to the size (in bits) of a memory data word or packet divided by the size (in bits) of a peripheral data word. The input/output unit reads the data at the requested memory location into an input buffer, combines the portions of that data not to be modified with the data provided by the peripheral, and sends the result back to the same memory location.

Abstract: In a parallel processor, a plurality of data processing nodes are intercoupled through an array of message routing circuits. Each message routing circuit has multiple input channels on which messages are received and multiple output channels on which messages are sent. A message on an input channel of any one particular message routing circuit contains a header followed by data with the header consisting of a sequence of control characters which route the data. Depending on the control character sequence that is received on an input channel, the data is sent to one, two, or three output channels and each such data transmission is preceded by a respective modified header which is generated from the header on the input channel. By sequentially performing this message processing in a series of message routing circuits, the data is delivered to multiple nodes along a tree-shaped path.

Abstract: An integrated circuit package includes an integrated circuit chip, a substrate which holds the chip, and a heat conduction mechanism which provides a path for conducting heat from the chip to a fluid medium; wherein the heat conduction mechanism is characterized as having a pressed joint which is comprised of: 1) a member that is made primarily of aluminum or copper, having a solid polysiloxane coating of less than 200.ANG. thickness, and 2) a liquid metal alloy in contact with the coating. This solid coating, on the aluminum or copper member, is fabricated without any expensive equipment by the steps of: 1) forming a liquid coating of a polysiloxane solution on the aluminum or copper member; and 2) baking that member with its liquid coating at temperatures of 100.degree. C.-300.degree. C. for 0.5 hours-3.0 hours. Thereafter the integrated circuit package is completed by placing the member with its solid coat in the heat conducting path such that a liquid metal alloy is in contact with the solid coat.

Abstract: Apparatus and method are provided for segmenting, parsing, interpreting and formatting the content of instructions such as air traffic control instructions. Output from a speech recognizer is so processed to produce such instructions in a structured format such as for input to other software. There are two main components: an instruction segmenter and a robust parser. In the instruction segmenter, the recognized text produced by the speech recognizer is segmented into independent instructions and each instruction is processed. The instruction segmenter receives a recognized air traffic control or other instruction, and segments it into individual commands. Utterances or other language are thereby broken up into their component instructions by detecting probable instruction boundaries. If normal processing fails, then robust backup processing is invoked, as a fallback after a fixed time per word has elapsed or a processing failure has occurred.

Abstract: An electronic data transmission system has a low peak-to-average power ratio by including a transmitter circuit which receives an input signal and in response generates a distorted output signal. This distorted output signal is generated such the output signal has a large magnitude when the input signal has a high probability of occurrence, and the output signal has a small magnitude when the input signal has a low probability of occurrence. The distorted output signal travels over a communication channel to a receiver circuit which regenerates the input signal by amplifying the distorted output signal with a gain that is the inverse of the gain by which the distorted signal is generated.

Abstract: The disclosed invention is a method in a computer peripheral control system for initializing and monitoring operations of a plurality of peripheral device controllers. The system includes more than one master controller. The method comprises the steps of storing in registers of the master controllers an initial set of parameters for operation of the control system, executing a self test of each of the master controllers to determine if any errors have occurred; and if so, checking to verify presence of a redundant master controller. The method further includes detecting whether or not the redundant master controller is in control; if not, setting bus active control signals; enabling active clock output signals; initializing status bus address pointer; polling a selected one of the peripheral device controllers; checking for end of cabinet address; incrementing status bus address pointer; and repeating the steps of initializing through incrementing.

Abstract: Two partitioned systems are interconnected by bus exchange modules which connect to first and second system common busses. Each system common bus shares three or more requestors, and an arbitration logic unit in each partition manages bus access priority depending on certain existing conditions. Equitable access to each system bus is allocated and no one particular requestor will be locked out from bus access. Deadlock and starvation are prevented by setting one requestor module for normal top priority but also allocating secondary priority to the remaining two requestor modules by toggling and rotating priorities among these two requestor modules. Additionally, the arbitration logic allows the two requester retrying modules to request the bus at a temporarily higher priority, but limiting the number of retry cycles allowed to any given requesting module.

Abstract: A maintenance interface system for testing the Logic states of circuitry in digital modules provides for selecting a snake data path and using its control to Write into or to Read out in a forward sequence or selectively in a reverse sequence.

Abstract: In a computer system having a user interface, a memory, a repository and a database, a repository program operating in the computer system for accessing the database, the repository program executing a method for supporting modeling, the method comprising the steps of examining a collection of types forming a model; sorting object types into data and persistent type objects; creating all data type objects and adding to a collection of all objects owned by the model; creating all persistent type objects and adding to a collection of all objects owned by the model; initializing all persistent type objects in the collection of objects.

Abstract: A lead-in guide and starting locator for use with a sheet metal card guide or similar structure is disclosed. The disclosed lead-in guide is preferably of a one piece construction and is most preferably molded or machined from a plastic material. The lead-in guide of the present invention provides multiple board lead-in slots and preferably includes integral retention pegs for quick mechanical attachment or can be held in place by a separate fastener. In a preferred embodiment, the lead-in guide has a top surface cut by a series of grooves that will be aligned with the slots in the card guide. Preferably, the lead-in guide has a front section that is somewhat thicker than the rest of the lead-in guide.

Abstract: An enhanced computer system architecture provides a processor supported by a general cache and a mini-cache wherein the mini-cache will supply requested data words not available in the general cache thus eliminating the extra clock periods necessary to access main memory. The mini-cache stores frequently used data words and is refilled concurrently during processor command execution and is settable for handling data words or code words or both. A data queue storage stores a block of words which duplicate words in main memory. If the requested address matches an address register block in the mini-cache, the data queue store will make the words in the data queue available to requests from the processor. The mini-cache also monitors the system bus for any "write" operations which might change the validity of the data in the address register block of the mini-cache. In this case, the data stored in the mini-cache is invalidated and cannot be used by the processor.

Abstract: A single integrated antenna feed transmits and receives electromagnetic waves in the C, X, and Ku frequency bands. This antenna feed includes an inner metal tube which lies along a central axis, and an outer metal tube which surrounds and is coaxial with the inner metal tube. Through the inner tube, a passageway is provided which is sized to carry electromagnetic waves in the X-band and Ku-band, but reject electromagnetic waves in the C-band. Between the inner tube and the outer tube, another passageway is provided which is sized to carry electromagnetic waves in the C-band. An I/O port for the X and Ku-bands is provided by a first end of the inner tube, and an I/O port for the C-band is provided by a corresponding first end of the outer tube. This first end of the outer tube lies proximate to but not past the first end of the inner tube. A solid dielectric is inserted into and fills the first end of the inner tube; and, a hollow metal cone is attached to the first end of the outer tube.

Abstract: A microcode cache memory is provided on a processor chip for supplying frequently used microcode instruction words to a processor. A bank of multiple Tag-Status RAMs holds addresses of microcode words residing in a bank of Data RAMs. A state machine and a special Least Recently Used Random Access Memory (LRU RAM) operate to maintain the more frequently used words in the Data RAMs so that more hits occur to provide the requested word in one clock cycle. A 90 bit microcode word with 20 fields enables the processor to perform multiple functions simultaneously in parallel.

Abstract: An electronic transmitter transmits multiple digital input signals simultaneously by including an encoding circuit, a digital combiner circuit, and a modulator circuit. The encoding circuit encodes each of the digital input signals as a sequence of "1" and "0" chips with all of the chip sequences being synchronized in parallel; the digital combiner circuit generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in the synchronized chip sequences; and, the modulator circuit generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of the signed multi-bit digital signal.

Abstract: A CDMA communication system is provided in which bit rates are dynamically allocated by a single CDMA receiving station to a plurality of CDMA transmitting stations, all of which are intercoupled to each other over a CDMA channel and a feedback channel. Each CDMA transmitting station includes a control circuit which sends control signals on the CDMA channel in spaced apart time intervals which request respective bit rates on the CDMA channel; and, the CDMA receiving station includes a bit rate allocating circuit which receives and responds to the control signals by sending feedback messages over the feedback channel that address individual CDMA transmitting stations and grant respective bit rates to the addressed station. In one preferred embodiment, each transmitting station includes a data buffer which stores a time varying number of data bytes that are to be sent, and each transmitting station requests respective bit rates on the CDMA channel by including that number in the control signals.

Abstract: The present invention is useful in a data processing system having a data processor coupled to a SCSI channel disposed for transmitting and receiving data between the data processor and a peripheral storage subsystem. The present invention is a method for controlling a bridge controller that permits expanding the maximum allowable number of disk drives connectable to the SCSI channel. In particular the method comprises the steps of receiving a command from the SCSI channel; initializing queue pointers from a memory in response to the command; determining the command type and setting flags and pointers in response thereto; when the command is a write operation, transferring data from the SCSI channel and storing the data in the memory; selecting a disk drive to receive the data by sending message and command bytes to the disk drive; and, transferring the data from the memory to the selected disk drive.

Abstract: The logic circuitry of an IC chip is connected to JTAG register chains which hold state information on each portion of the logic circuitry therein. A JTAG Tracker Module is connected to the controls of each of the JTAG register chains enabling a programmer-operator to read the present state of each JTAG register chain and enabling a readout of the logic circuits condition in a single clock period.

Abstract: By expanding the cache address invalidation queue into bit slices for holding odd invalidation addresses and even invalidation addresses and also by providing a more efficient series of transition cycles to accomplish cache address invalidations both during a cache hit or a cache miss cycle, the present architecture and methodology permits a faster cycle of cache address invalidations when required and also permits a higher frequency of processor access to cache without the processor being completely locked out from cache memory access during heavy traffic and high level of cache invalidation conditions.