Abstract: A data processing array is partitioned by electronic control signals into multiple sub-arrays which are established and operate independently of each other. In the preferred embodiment, an operator's console is provided for manually selecting the data processing nodes that are in each sub-array, and a control module is coupled by control channels between the console and the data processing nodes. These control channels carry the control signals directly to the data processing nodes without utilizing the input/output channels which are intercoupled to form the array. One portion of these control signals prevent each node in a sub-array from sending messages on the input/output channels to any node in another sub-array; and another portion of the control signals select a node in each sub-array as a boot node from which a separate operating system and user programs are loaded without utilizing the input/output channels.

Abstract: A system and method for using standard JTAG protocol for testing protocol compliant and non-protocol compliant digital devices without altering the JTAG protocol or the non-compliant device. A specialized Test Access Port Controller controls and monitors the states applied to the non-compliant device in order to eliminate the PAUSE state in the non-compliant device and to limit the Run-Test/Idle state to one clock period.

Abstract: A digital system which normally initializes and tests non-JTAG logic units is adapted to test JTAG protocol compatible logic units. A JTAG translator unit provides an instruction control register and a Data Register. The Control Register has control bits for selecting Test-Mode-Select and Test Clock signals for the JTAG compatible units and Shift/Hold signals for the non-JTAG compatible logic units. The Data Register supplies diagnostic test bits to registers in both the JTAG and non-JTAG logic units. Additionally, the Control Register can initiate automatic incrementation of addresses to a control state RAM for rapid loading of microcode.

Abstract: A system whereby a microcode RAM in a central processing module can have each microcode word rapidly accessed and transferred to a maintenance controller to compare each accessed microcode word with a corresponding microcode word in a set of microcode words which were pre-loaded in a flash memory.

Abstract: An arbitration logic system in a system control module regulates access to a common system bus as provided by a state machine which toggles access priority between two or more resource modules while preventing deadlock contention between two requesting modules while insuring that no module will be starved or denied access even though all the resource modules are contending for bus access. Any continuous deprivation or starvation of a module for bus access is prevented, in addition to any deadlock situations which are also prevented. This occurs by allowing retrying modules to request the bus at a temporarily higher priority and limiting the number of retries that any given requesting module is permitted to have.

Abstract: The method of the present invention is useful in a computer system having a user interface, a memory, a repository and a database. The method is a repository program executed by the computer system for locating a versioned object within a history of objects stored in the repository.

Abstract: A central processor is serviced by a multi-way cache module having N cache sets some of which can be taken off-line by a maintenance subsystem. Masking logic is provided to control the fill-operation cycles to cache so that equitable distribution of fill-data is allocated among only those cache sets remaining on-line.

Abstract: A system for interleaving invalidation cycles to a cache memory during those periods when the processor is waiting or has not need to access cache memory. These periods occur during a Read-Miss operation or when bus access delays to main memory cause the processor to wait for receipt of data, or when the processor communicates with network modules other than the cache memory and main memory.

Abstract: A data processing system includes a digital computer that has a plurality of data processing programs. A set of upgraded stations is coupled to the computer which generate messages that employ a relatively simple format to select the data processing programs; and a set of older stations is also coupled to the computer which generate messages that employ a complex format to select the data processing programs. A message routing program in the computer receives all of the messages from the stations, analyzes each message that has the simple format to identify the selected data processing program, and sends the message directly to the selected program. By comparison, the message routing program sends each message that has the complex format to a secondary routing program; and this secondary routing program analyzes each message which it receives, identifies the selected data processing program, and sends the message to the selected program.

Abstract: A state machine system is used to control a cache controller in a network involving the operations of a processor having a store-through cache and operations involving an invalidation queue which is filled by a spy module which monitors dual system busses to select addresses of words which appear for write operations.

Abstract: An electronic transmitter for a digital communication system which eliminates cumulative jitter is comprised of an input port on which a continuous input stream of data bits is received at a transmitter input bit rate. Also, the transmitter includes an output terminal on which a continuous output series of bits are transmitted, at a transmitter output bit rate that is faster than and independent of the transmitter input bit rate. This output series of bits consists of the input stream of data bits partitioned into spaced apart data blocks, with a respective output header inserted before each block.

Abstract: An electronic receiver for a digital communication system which eliminates cumulative jitter is comprised of an input circuit which receives a continuous series of bits, on an input terminal, at a receiver input bit rate. This series of bits consists of data bits in spaced apart data blocks, with respective headers that have a variable length and fill the space between the data blocks. Also, the receiver includes an output circuit, which is coupled to the input circuit. This output circuit sends selected bits from the data blocks, but not from the headers, to an output port at a receiver output bit rate which is slower than the receiver input bit rate. Further, the output circuit includes a closed loop feedback control circuit, which selects the receiver output bit rate, such that it is substantially constant and such that the selected bits from the data blocks occur on the output port as a continuous bit stream.

Abstract: A FIFO invalidation queue for address words, from a spy module, are held for subsequent invalidation operations to a cache memory. The FIFO queue is programmably organized to indicate when it is almost full in which case it will switch to a priority operation which will give priority to invalidation cycles in the cache over the priority of the processor's cache access. When the FIFO queue indicates that it is almost empty, then the priority of the cache access by the processor is re-established as it was in normal conditions. The system operates concurrently in a self-regulating manner to load and unload addresses into the FIFO queue while also giving priority to flushing out the queue with invalidation cycles when preset upper limits are reached.

Abstract: A memory cell includes a pair of spaced apart conductors on an insulating layer, and a novel electrically alterable resistive component between the conductors. This resistive component consist essentially of Germanium, having a crystalline grain size which is smaller than polycrystalline; and the Germanium switches from a high resistance to a low resistance upon the application of a threshold voltage across the conductors.

Abstract: An electronic repeater for a digital communication system which eliminates cumulative jitter is comprised of an input terminal on which a continuous input series of bits is received, at a repeater input bit rate. This input series of bits constitute an interleaved bit-serial sequence of input headers and data blocks. Also, the repeater includes an output terminal on which a continuous output series of bits are transmitted, at a repeater output bit rate that is not equal to and is independent of the repeater input bit rate. This output series of bits constitute an interleaved bit-serial sequence of output headers and the received data blocks.

Abstract: A communication system which eliminates cumulative jitter is comprised of a transmitter which receives a continuous input stream of data bits at a transmitter input bit rate on an input port, and which simultaneously transmits the data bits in spaced-apart bit-serial data blocks with respective bit-serial headers that have a variable length and fill the space between the data blocks. Also, the communication system includes a receiver, coupled to the transmitter, which receives the spaced-apart data blocks, and which simultaneously generates from selected bits in the received data blocks but not the headers, an output stream of the data bits at a receiver output bit rate on an output port.

Abstract: In accordance with the present invention, a high speed two-part storage interface unit includes--1) a primary I/O port (input/output port) that couples to a plurality of data processing modules; 2) a secondary I/O port that couples to a main memory module, 3) input circuits for receiving three types of write commands and one type of read command from the data processing modules, 4) several write execution modules which are serially-coupled to a time-shared memory, and 5) a control circuit by which the write commands and read commands are performed.

Abstract: A field programmable gate array circuit device provides a bus interface data path between a processor and system bus, each of which operates at a different data transfer protocol at a different clock rate. The bus interface unit controls the transfer of data to and from a system bus which is connected to a main memory module, an I/O module or other modules, such as an external CPM module. Data passing from various modules to the processor or from the processor to various modules can operate in one word or four-word blocks. Additionally, intermodule communication is managed by message words, which message words are operative in groups of four words as a block. A transfer logic box holds a plurality of (i) Request words (ii) Acknowledgement words for conveyance to the processor from external modules.

Abstract: A first set of input index signals represents a row-column array of quantized pixels; and each input index signal in the first set represents a rectangular non-overlapping quantized pixel group which is aligned to a particular row and a particular column. By repeatedly performing three steps on different pairs of the input index signals in the first set, a second set of index signals is generated wherein a respective index signal exists for each individual pixel in the array and by which the image can be filtered. These three steps are: 1) selecting a pair of input index signals in the first set such that the two quantized pixel groups which the selected index signals represent are adjacent to each other in the array; 2) forming an address signal by combining the two selected input index signals; and 3) reading a memory with the address signal to thereby obtain an output index signal.

Abstract: The method of the present invention is useful in a computer system having a user interface, a memory, a database and a repository operative in the computer system for accessing the database. The method is implemented by the computer system for collapsing a version tree that depicts a history of objects stored in the database. The method, which is stored in the memory at run-time, comprises the steps of validating collapse request by insuring that the target object is not a ghost object, the end object is not a ghost, the end object is on the same version tree as the target object, and the end object is a later version than the target object. An empty array representing path objects is initialized from the target object to the end object; and if an end object is supplied, a function is called to build up an array of objects representing paths from the target object to the end object. The array of objects built up in the preceding steps is processed.