Abstract: A two-way set associative cache memory system for a parallel-pipelined computer system uses separate queue structures to hold main memory fetch and store requests generated by the central processing unit (CPU). A memory access unit, coupled between the cache memory system and the CPU selects the next request to be processed by the main memory from between the requests at the heads of the fetch and store queues. The request at the head of the fetch queue is preferred over the request at the head of the store queue unless the memory partition to be used by the fetch request is still busy with a previous request while the partition to be used by the store request is idle. Data retrieved from the main memory replaces data in the cache according to an algorithm that prefers empty pages within a set to pages that contain data and prefers pages that do not have pending update requests scheduled to pages that do have pending update requests scheduled.

Abstract: A novel high speed unidirectional bus system is provided for receiving a plurality of novel circuit card assemblies in receptacles on the bus. Adjacent receptacles are connected by lines on the bus which interconnect output pins to input pins. The circuit between output pins and input pins are formed by connecting the plugs on circuit card assemblies into the receptacles on said bus. The system comprises a plurality of function circuit card assemblies connected in a daisy chain when inserted into adjacent receptacles on said bus between a source circuit card assembly and a destination circuit card assembly and the address portion of the information supplied by the source circuit card assembly is programmed to identify the function circuit card assembly to first receive the source data whereby the unidirectional bus system may be operated in a time division random access mode at data rates in excess of the data rates of individual functional circuit card assemblies.

Abstract: This is a computer-implemented model for the frequency space utilized by the Mode Select Beacon System (the Mode S system) for air traffic surveillance and control. The model simulates the operation of interrogators, transponders, and receivers, and calculates the probability of interference between transponder reply signals using a sliding window.

Abstract: An improved phase locked indication circuit for a Costas QPSK carrier recovery loop comprises an inphase channel, a quadrature channel and phase error channel each connected to an input of a three input summing circuit through a diode square law multiplier and wherein the error channel signal is filtered by a low pass filter to smooth the signal before being applied to the negative input of the summing circuit to diminish false lock and not locked signals. The locked and not lock conditions are separated one from the other by a large signal to noise ratio.

Abstract: A transmitter is provided which simultaneously transmits waveforms such as with different data rates. These transmissions are modulated (e.g. phase modulated) onto quadrature channels of a common carrier, and are then combined. The resulting composite modulated waveform is upconverted to RF, power amplified, split and routed to separate ports for transmission. The transmitted signals are then received, downconverted and demodulated to produce the original signals.

Abstract: Multiple clocks are interconnected in a network which is fed and controlled by a clock generator. A delay of one or more clock periods less a fixed amount is imposed between any two such clocks excluding the clock generator, to cause the repeated clock so transferred to occur at the appropriate time in the next cycle. Feedback using such delays assures bounded phase differences among these clocks. Thus, skew bounds can be provided for large numbers of clocks, to provide a bounded delay among multiple clocks. There is inserted in each link between a pair of clock nodes a delay line that delays a propogating clock signal by just enough time to cause the repeated clock to occur at the appropriate time in the next cycle, thereby synchronizing the appearance of that clock signal at the various nodes. Self-oscillation of the system, if the clock generator is removed, is avoided by having the delay between any two directly connected nodes be greater than one period of that clock generator.

Abstract: A brightly colored underwater signaling device having a brightly colored watertight container filled with one or more freely-movable spherical objects. Vigorous displacement of the container causes the spheres to collide with and impact both each other and the inner wall of the container to produce an audible rattling sound with a pitch, timbre and intensity which is easily transmitted through water. The device is preferably constructed of PVC pipe containing a plurality of ball-bearings and connected to a skin diver's diving apparatus with a connecting strap.

Abstract: An improved interface unit for receiving a stream of parallel bit words from a source bus comprising an address field, a data field and a clock field. The parallel bit words are first phase adjusted and stored in an input register where the address field is compared in enable logic to determine whether to store the data field in a sink buffer register for processing. The word in the input register is coupled to the buffer storage register. The address field is further compared in pass through disable logic to determine whether to pass the address and data field to an output register or to generate a null code address in the address field of the word being outputted from the buffer storage register. The word in the buffer storage register is coupled through a word selector to an output register.

Abstract: A mainframe computing system is adapted to be loaded with one of a plurality of different operating systems and different associated microcode to provide a computing system which is capable of running user programs adapted to be executed by the loaded operated system comprises a main memory for receiving the desired operating system coupled to a system bus. An instruction processor and an input/output control processor are coupled to the system bus and are provided with an instruction register for presenting user program instructions to the processors. The processor means have associated therewith microcode storage memory which receive and store a set of microcode instructions to be performed by the processors according to the program instruction stored in the instruction register. The stored microcode comprises primary microcode instructions to carry out each of the instructions in the instruction register means.

Abstract: An image processing station 18 displays data indicative of a plurality of document on a monitor 22 from data stored in a main image store 16 and the image processor 18 accepts commands from a keyboard 26 to print the images or to retrieve a new document from the main store 16 or a video memory 50 which comprises selectable first 56 and second 62 page portions either of which may be loaded with fresh image data while the other page portion is being displayed and documents are swapped from one page to the other when fresh document images are moved into one of the pages.

Abstract: A novel programmable digital gain controller is provided for the automatic gain control loop of a communications receiver. The digital gain controller comprises a pair of digital detectors coupled to the real and imaginary components of a data stream for providing digital data magnitude output signals which are coupled to an adder whose output is coupled to a first input of a comparator having a second input coupled to a predetermined reference level command. The output of the comparator generates a digital error signal which is coupled to the input of a programmable gain accumulator having a second input proportional gain command so as to provide at the output of the programmable gain accumulator a digital gain command which may be coupled to a variable gain controlled amplifier which is connected in the input data stream of the channel of a communications receiver to provide a predetermine amplifier output level.

Abstract: The present invention provides a novel programmable data communications controller employed to accept data from a host computing system and for transmitting the data to a terminal designated by the host computer system. The data computer communications controller is further provided with protocols, parameters and poll tables stored in a dedicated memory of the data communications controller which enables the controller to receive data and address information from a main memory of a host computer and to reformat and pre-package the information in a protocol format block acceptable by a terminal coupled to the data communications controller. Different protocols, parameters and polls are provided in the data communications controller in the form of preprogrammed information which enables different terminals employing different protocols and protocol formats to be coupled directly to a data link interface bus without hardware modifications.

Abstract: A novel high-speed bit synchronizer circuit comprises a phase detector having two phase detecting loops, each adapted to generate a partial error voltage signal which is summed together to provide a single phase voltage error signal which is employed to control a VCO in the return branch of both phase detecting loops. Each phase detecting loop comprises a comparator coupled to the input data stream and to a reference voltage to provide two outputs. An electronic switch is coupled to the output of each comparator and each switch has its partial error voltage output coupled through a summing circuit to the VCO, thus completing two phase detecting loops each adapted to generate a partial phase error signal indicative of the phase error between the input data stream and the recovered clock output of the VCO.

Abstract: In a communications data link network of the type having a plurality of ground stations and a single moving airborne station, there is provided a doppler frequency compensation circuit in each of the ground stations. The downlink carrier frequency is fixed and continuously broadcast to the receiving ground station which continuously receive the doppler shifted carrier signal. The ground stations are provided with coherent demodulators which provide a coherent I.F. recovered carrier signal that is applied to a scaling phase-locked loop to provide a deviation frequency signal that is applied to an inverting phase-locked loop which provides a pre-compensated uplink R.F. carrier signal. The uplink R.F. carrier signal has a compensated uplink doppler frequency component which equals the inverted and scaled doppler frequency of the received downlink carrier.

Abstract: A programmable digital gain accumulator is provided with a digital accumulator having approximately the same number of significant bits as the input data stream. The most significant bit of the input data stream is a sign bit coupled to a series cascade of flip-flops providing a selectable plurality of flip-flop delay times. The carry output of the accumulator is coupled to an input up/down counter having its output coupled to a multiplexor capable of selecting one of the carry outputs of the input up/down counter. The up or down count is controlled by the sign bit input from the sign bit delay circuit. The output of the multiplexor is inputted to an output up/down counter whose parallel output is the parallel synchronous digital gain command signal for direct use by a utilization device. The up or down count of the output up/down counter is controlled by a delayed sign input from the sign bit delay circuit.

Abstract: A programmable second order loop filter is provided with first and second programmable scaling circuits arranged in parallel and having their outputs connected to first and second programmable one bit serial adders respectively. The output of the second programmable serial adder is coupled to the input of said first programmable serial adder and has its output coupled to the input of a programmable output stage so as to provide the ability to maintain the average quantization bit error to one-half of one bit of the least significant bit of the full loop filter width even though the output does not use or employ all of the significant bits.

Abstract: An integrated priority network is provided for a bus architecture computing system of the type employing a M-Bus connected to a plurality of functional elements. Each functional element has its own integrated priority resolution network (IPRN) coupled to said M-Bus for activating its own unique individual priority request and for receiving all individual priority requests from all other functional elements. Each integrated priority resolution network unit is provided with a rotational priority circuit and a preemptive priority circuit connected in parallel and operable independently to produce a request granted signal. Logic circuits in each rotational priority circuit determine when an IPRN unit will be granted its priority request for access to said M-Bus and will block future requests from being activated to its IPRN unit until the other IPRN unit values in the rotational priority register of the rotational priority circuit have been granted access to said M-Bus.

Abstract: The present system is employed to generate and transmit information which is needed to construct or assemble truth tables and pertinent data which are directed to associated circuits which require testing. The present method employs a technique whereby information is nested, or compacted, in accordance with certain rules of grammar and is transmitted from a circuit design group to a vendor, i.e., a manufacturer of the circuit designed by a design group. When the nested information is expanded by a translator device, or by a translation program, at the manufactuer's location, it is directly expandable into truth table information for use by various logic testers. Each of the truth tables defines a specific function that the designer wants tested in the associated circuit. The manufacturer supplies the test platform hardware which generates the desired signal patterns defined by the truth table information and pertinent data.

Abstract: An individual integrated circuit package utilizing an intermediate die carrier having legs in contact with a wiring substrate and a compatible lid to effect hermeticity. More specifically, the carrier includes on its outer surface a raised section and a peripheral ledge. The cap is formed with a cutout in its closed extremity to accommodate the raised carrier section and the portions of the cap adjacent the cutout rest upon and are sealed to the carrier ledge. The rim of the cap at its open extremity contacts and is sealed to the substrate to form the completed hermetic package.

Abstract: A binary encoder for vector quantization is provided which comprises a plurality of identical two-level branch selectors connected in a turnaround cascade pipeline array. The upper levels of the two-level selectors are connected in series and the first selector receives a formatted digital data vector input. The upper level of last selector has its output connected to its own lower level input and the outputs of the lower level selectors are connected in series so that the last lower level selector in the turnaround cascade resides in the first two level selector. The output of the last lower level selector provides a desired compressed data vector output.