Abstract: The invention provides internal self testing within an integrated circuit chip at all points along the logic chain. Internal stimulus generators and supervisory control circuits for the generators formed integrally within a VLSI chip are utilized together with integrally formed multiple fault detectors to provide self testing of the logic chain, mechanical interconnection failures, and power and clock pulse checking. The invention is utilizable in conjunction with either single or duplicate logic, which latter may be either duplicate complementary logic or duplicate functional logic. The multiple fault detectors provide a multiplicity of error signals which are multiplexed within the chip to produce encoded output error signals each of which designates the fault which has been detected within the chip. The invention eliminates the need for sophisticated ancillary test systems for diagnostic and go/no-go or confidence testing for hardware at the chip, board and system level.

Abstract: A low-cost printer is provided for use with data processing equipment. A light-shielding retainer provides a substantially continuous sheet supply of printing medium including a conductive-resistant coating formed in strips which is light sensitive and heat developed. The medium is moved past a processing station. A first portion of the station includes an array of light emitting elements and a second portion includes an element for heating the medium sufficient for developing the medium thus visibly exposing and fixing the characters on the medium.

Abstract: A method of fabricating a "hybrid" multilayer printed circuit board combining two dissimilar plastic layers of polyimide resin/glass and of epoxy resin/glass laminates. The finished hybrid multilayer printed circuit board is for, e.g., the support of and electrical interconnection to a plurality of magnetizable memory cores. The method includes sandwiching a plurality of epoxy-glass printed circuit boards having the desired copper patterns on both sides between two polyimide-glass printed circuit boards, each having the desired copper pattern on only one side. All the printed circuit boards are laminated with epoxy-glass prepreg to form a single hybrid multilayer printed circuit board consisting of the sandwiched epoxy-glass printed circuit boards and the sandwiching polyimide-glass printed circuit boards. Interconnections between patterned layers are formed by copper-plated through-holes.

Abstract: Apparatus is disclosed for positioning a continuous paper form having uniformly positioned seams and emanating from a high speed printing device, such as from a high-speed computer printer, in a bin or stacker. Air jets positioned on the stacker are utilized in a mode whereby air bursts from the jets impinge at discrete locations on a top surface of the form as it emanates from the printer. The air bursts cause the continuous paper form to fold naturally in a stacker bin at the paper seams.

Abstract: An apparatus comprising a rotating substrate holder is provided. The rotating substrate holder is hollow and adapted to receive liquid gas such as nitrogen to cool the substrate to cryogenic temperatures. The novel substrate holder is supported inside of a vacuum chamber by a thin wall tube which is sealed with a liquid rotating seal at the point where it passes completely through the top wall of the vacuum chamber. The novel thin wall tube support provides access to the hollow substrate holder from outside the vacuum chamber and provides temperature isolation of the liquid in the substrate holder so that the liquid rotating seals are maintained at operable elevated temperatures.

Abstract: A single Josephson junction device is arranged in a single branch which comprises an external source resistor connected in series with an output resistor and a Josephson junction device. An input node and an input resistor are in series and connected to the node between the output resistor and the Josephson junction device. Voltage signals applied to the input voltage node are amplified by connecting a high gain voltage output in parallel with the output resistor and providing sensing means for sensing the voltage output across the output resistor only when the Josephson junction device is switching from its low impedance state to its high impedance state.

Abstract: An improved method of anodization of thin films for the fabrication of superconducting devices. An electrically conducting contact layer is formed over a substrate between an electrically conducting object layer and the substrate. Also, an electrically insulating layer is formed between the object layer and the contact layer. The contact layer is connected to a power supply and at least a preselected portion of the object layer is anodized to a predetermined thickness. This may include anodizing all of some preselected portions through the complete thickness of the object layer. A pattern of hardened photoresist on the object layer provides portions not protected by the pattern. When anodization of the electrically conducting object layer takes place, the resulting anodized portion is thicker than the thickness of the portion of the object layer that it replaces.

Abstract: During the manufacture of Josephson superconducting devices, it is necessary to provide on a substrate a base electrode, a counter electrode and a small tunnel barrier area therebetween. A novel method of making all three of these active elements in the same vacuum chamber without having to remove the substrate from the vacuum chamber is provided so that the tunnel barrier area is accurately made to a predetermined size and without the danger of contamination. The novel structure is made as a substantially planarized laminate in the vacuum chamber and the tunnel barrier area is defined in a supplemental step.

Abstract: In a high speed data processing system, there is provided a circuit for shifting either right or left as data is transmitted to or from the main storage unit. Apparatus for high speed parallel byte shifting is connected to the data bus which connects the main storage unit to the system and comprises logic which selects predetermined byte lines. Information from the individually selected byte lines is temporarily stored in parallel buffer registers and subsequently returned to a different byte line to provide byte shifting without the requirement of shift registers or complex logic.

Abstract: An apparatus for and a method of correcting chromatic aberration in a multiwavelength input light beam deflection system incorporating a magneto-optic diffraction grating is disclosed. The diffraction grating generates a chromatic aberration induced plurality of first order light beams from the multiwavelength input light beam, each different wavelength light beam being deflected a correspondingly different angle .lambda. by the diffraction grating. Correction plates, designed to provide zero chromatic correction for a wavelength .lambda..sub.o with corresponding positive and negative chromatic correction for wavelengths about the wavelength .lambda..sub.

Abstract: An intelligent terminal is provided having a small number of dedicated function keys, a telephone numerical key pad and an elongated visual line display mounted on a small flat terminal housing. Activation of the system causes the associated micro processor in the terminal housing to present a plurality of functions on the line display. Depression of a function key which is opposite one of the functions and dedicated to the key generates a signal indicative of the function key being depressed. The micro processor is programmed to present a different and new set of functions to said line display each time a function key is depressed until a result or answer is finally presented on said line display.

Abstract: The present invention teaches a method of planarizing built-up vacuum deposited surfaces or areas on Josephson junction and semiconductor devices so that successively deposited layers do not replicate the undulations of previous layers. After a surface layer is deposited in a vacuum system and part of the surface is etched, a raised surface is generated. A photoresist lift-off stencil is applied to the surface to be preserved and the material to be removed is removed by isotropically etching so as to leave an overhang or ledge of photoresist material over the area of the material retained. A new layer of material is now deposited by vacuum deposition so as to almost fill the area to be planarized. A small gap remains between the top of the new material being vacuum deposited and the botton of the photoresist stencil so that solvent can be introduced to the stencil. When the photoresist stencil is removed, the top of surface being preserved is substantially planar with the new layer of material.

Abstract: A Josephson junction AND gate logic circuit is provided which has an enhanced and improved operating window area. The circuit comprises two parallel branches one for the input and one for the output connected between a biasing current source and a ground or reference voltage. The input branch is provided with a first branch resistor, a third Josephson junction and an interferometer in series between the current source and ground. A plurality of input gate signal lines connects to the interferometer and a sink resistor is connected in parallel with the interferometer. When the input current signals collectively exceed a predetermined level, the two Josephson junctions in the interferometer switch ON and assume the high impedance state. The input current and biasing current is diverted into the output branch causing the second Josephson junction in the output branch to switch ON.

Abstract: A two branch, three Josephson junction gating circuit is provided with a plurality of inputs to enable the circuit to be operated as a high-gain logic OR gate. The circuit is arranged to provide a larger operating window area and to provide an improved and optimized gain characteristic by selectively switching ON the Josephson junctions in the circuit.

Abstract: A high speed gallium arsenide (GaAs) integrated circuit is provided which converts GaAs input or source signals to voltage levels for directly driving emitter coupled logic (ECL) circuits. The high speed GaAs level converter comprises a level shifting network at the input, two stages of differential amplification and a novel source follower output stage.

Abstract: An adjustable support for a display terminal is provided which comprises a novel moulded base element having a pair of concave tracks in the top and an annular recess in the bottom. The concave tracks in the top of the base are adapted to receive and support a moulded cradle element which serves as a housing for the CRT display. The annular recess in the bottom of the base receives an annular support ring which is adapted to support the base and the cradle. The three moulded elements are designed to fit together and maintain contact with each other by gravity so as to provide a low cost accurate adjustable support.

Abstract: The present invention provides a high-speed low-power gallium arsenide basic logic circuit which is capable of being driven by either emitter coupled logic or gallium arsenide logic level signals to provide combinational logic gating such as OR-AND, OR-NAND, OR-AND-OR and OR-AND-NOR capable of driving directly either emitter coupled logic or gallium arsenide logic circuits. The combinational logic gating is basically accomplished by diode logic which performs other functions and which requires less area on an integrated circuit chip than active switching transistors.

Abstract: An x-ray mask is made by forming a thin polyimide membrane on a silicon wafer substrate which is then back-etched to form a mask supporting ring of the substrate.

Abstract: The invention relates to a tamper-resistant lock. The improved lock incorporates metal wafers which rest on the bottom pins in the inner cylinder of a cylindrical key lock. The wafers and the pins upon which they rest alternately incorporate holes in their topside. The wafers and the bottom pins cooperate with trap pins housed in the outer cylinder of the lock at a 45.degree. angle from the vertical insertion position of the key. The trap pins are urged into the holes in the wafers and bottom pins when tampering occurs. This apparatus prevents both the picking or impressioning of the lock, common alternative techniques for opening a key lock without the key. The improved lock also incorporates a feature to prevent unauthorized opening by rapid spinning of the lock by a spring-propelled insert placed into the lock cylinder after it has been picked.

Abstract: Disclosed is a monitor apparatus which can be worn by a patient and will provide an indication of activity levels over a number of subsequent time periods. A transducer which is energized by the ambulatory subject's movement, provides an activity pulse into a temporary memory. At the end of a standard timing interval, for example fifteen (15) minutes, a digital code word representative of the total number of activity pulses in that standard timing interval is fed into a solid state memory. The temporary memory is then reset and counts the activity pulses over the next standard timing interval. In this manner, activity levels for any number of sequential time intervals can be recorded without hindering the patient's movement. A contol logic circuit, which is externally triggered, causes the permanent memory to sequentially readout the activity levels of subsequent standard timing intervals for use in studying the activity levels of ambulatory subjects.